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參數(shù)資料
| 型號(hào)： | ASM1232LPSN-2 |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 5V uP Power Supply Monitor and Reset Circuit |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 276K |
| 代理商： | ASM1232LPSN-2 |
4 of 10
Notice: The information in this document is subject to change without notice
5V μP Power Supply Monitor and Reset Circuit
ASM1232LP/LPS
January 2005
rev 1.5
When PBRST is held LOW for the minimum time t
PB
, both
resets become active and remain active for a minimum time
period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20ms. No external pull-up resistor is required,
since PBRST is pulled HIGH by an internal 40k
resistor.
The PBRST can be driven from a TTL or CMOS logic line or
shorted to ground with a mechanical switch.
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. The μP must toggle the ST input within a set
period (as selectable through TD input) to verify proper
software execution. If the ST is not toggled low within the
minimum timeout period, reset signals become active. In
power-up after the supply voltage returns to an in-tolerance
condition, the reset signal remains active for 250ms
minimum,
allowing
the
power
microprocessor to stabilize. ST pulses as short as 20ns can
be detected.
supply
and
system
Timeouts periods of approximately 150ms, 610ms or
1,200ms are selected through the TD pin.
The watchdog timer can not be disabled. It must be strobed
with a high-to-low transition to avoid watchdog timeout and
reset.
TD Voltage level
Watchdog Time-out Period
(ms)
Min
Nom
Max
GND
62.5
150
250
Floating
250
610
1000
V
CC
500
1200
2000
~
~
V
OH
V
OL
RESET
RESET
PBRST
t
PB
t
PDLY
V
IL
V
IH
t
RST
Figure 3: Timing Diagram: Pushbutton Reset
PBRST
TD
TOL
GND
V
CC
ST
RESET
RESET
1
2
3
4
5
6
7
8
μP
RESET
5V
ASM1232LP/LPS
Figure 4: Application Circuit: Pushbutton Reset
~
Valid
Strobe
Valid
Strobe
Invalid
Strobe
ST
RESET
t
RST
t
ST
t
TD
(min)
t
TD
(max)
Figure 5: Timing Diagram: Strobe Input
Note: ST is ignored whenever a reset is active
PBRST
T
D
TOL
GND
V
CC
ST
RESET
1
2
3
4
5
6
7
8
μP
RESET
5V
ASM1232 LP/LPS
Figure 6: Application Circuit: Watchdog Timer
Decoder
Address
Bus
MREQ
10k
I/O
相關(guān)PDF資料 |
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| ASM1232LPUF | 5V uP Power Supply Monitor and Reset Circuit |
| ASM1232LPSN- | 5V uP Power Supply Monitor and Reset Circuit |
| ASM1232LPSNF | 5V uP Power Supply Monitor and Reset Circuit |
| ASM1232LPU | KJ SERIES II |
| ASM1232LPUN | 5V uP Power Supply Monitor and Reset Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM1232LPSN-2F | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:5V μP Power Supply Monitor and Reset Circuit |
| ASM1232LPSNF | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V uP Power Supply Monitor and Reset Circuit |
| ASM1232LPU | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V uP Power Supply Monitor and Reset Circuit |
| ASM1232LPUF | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V uP Power Supply Monitor and Reset Circuit |
| ASM1232LPUN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V uP Power Supply Monitor and Reset Circuit |
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