參數(shù)資料
型號: ASM1232LPSN-2
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: 5V uP Power Supply Monitor and Reset Circuit
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: SOIC-8
文件頁數(shù): 3/10頁
文件大?。?/td> 276K
代理商: ASM1232LPSN-2
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Notice: The information in this document is subject to change without notice
5V μP Power Supply Monitor and Reset Circuit
ASM1232LP/LPS
January 2005
rev 1.5
Detailed Description
The ASM1232LP/LPS monitors the microprocessor or
microcontroller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push-pull output stage and is the logical opposite to RESET.
RESET is an active LOW signal. It is developed with an open
drain driver. A pull up resistor of typical value 10k
to 50k
is
required to connect with the output.
Trip Point Tolerance Selection
The TOL input is used to determine the level V
CC
can vary
below 5V without asserting a reset. With TOL conected to
V
CC
, RESET and RESET become active whenever V
CC
falls
below 4.5V. RESET and RESET become active when the
V
CC
falls below 4.75V if TOL is connected to ground.
After V
CC
has risen above the trip point set by TOL, RESET
and RESET remain active for a minimum time period of
250ms. On power-down, once V
CC
falls below the reset
threshold RESET stays LOW and is guaranteed to be 0.4V or
less until V
CC
drops below 1.2V. The active HIGH reset signal
is valid down to a V
CC
level of 1.2V also.
Application Information
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override
the internal trip point detection circuits and issue reset
signals. The pushbutton input is debounced and is pulled
HIGH through an internal 40k
resistor.
Tolerance
Select
Tolerance
TRIP Point Voltage
(V)
Min
Nom
Max
TOL = V
CC
4.25
4.37
4.49
TOL = GND
5%
4.5
4.62
4.74
~
~
~
V
OH
V
OL
t
RPU
RESET
RESET
V
CCTP
(MIN)
V
CCTP
(MAX)
V
CCTP
t
R
V
CC
Figure 1: Timing Diagram : Power Up
~
~
~
V
OH
V
OL
V
CCTP
(MAX)
V
CCTP
V
CCTP
(MIN)
RESET
Figure 2: Timing Diagram : Power Down
RESET
t
F
V
CC
t
RPD
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