參數(shù)資料
型號: AS9C25512M2018L-200FC
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: TERM. F/O CABLE SC-SC/ DPLX/RISER/2M/RED
中文描述: 512K X 18 DUAL-PORT SRAM, 7.5 ns, PBGA208
封裝: FBGA-208
文件頁數(shù): 23/30頁
文件大?。?/td> 1100K
代理商: AS9C25512M2018L-200FC
AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 23 of 30
IEEE 1149.1 Serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan Test Access Port (TAP). All JTAG pins operate using JEDEC standard 2.5V I/O logic levels.
In order to operate the device without using the JTAG feature, all JTAG pins may be left unconnected. On power-up, the device will start in
a reset state which will not interfere with normal device operation.
TAP Controller block diagram
Note:
1. x = 111
JTAG timing waveform
Selection
Circuitry
Selection
Circuitry
3130 29
Identification Register
0
1
2
.
.
.
Boundary Scan Register
1
Bypass Register
Instruction Register
x
[1]
0
1
2
0
1
2
0
. .
. . .
TDI
TMS
TCK
TDO
TAP Controller
3
TEST CLK
TCK
TRST
t
JCYC
TMS/TDI
TDO
t
JCH
t
JCL
t
JIS
t
JIH
t
JOH
t
JCD
t
JRS
t
JRR
Don’t care
Undefined
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS9C25512M2018L-200FI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-200TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-200TI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-250BC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-250BI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface