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| 型號： | AS9C25512M2018L-200FC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | TERM. F/O CABLE SC-SC/ DPLX/RISER/2M/RED |
| 中文描述： | 512K X 18 DUAL-PORT SRAM, 7.5 ns, PBGA208 |
| 封裝： | FBGA-208 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 1100K |
| 代理商： | AS9C25512M2018L-200FC |
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AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 18 of 30
Collision detection
Three different cases of collisions can be listed depending on the type of access from two ports:
Simultaneous Read
: A true dual-ported memory cell allows data to be read simultaneously from both ports of the device. Hence no data is
corrupted, lost, or incorrectly output, and none of the collision alert flags is asserted.
Simultaneous Write
: When both ports are writing simultaneously to the same location, both write operations would fail. Therefore, the
collision flag is asserted on both ports.
Simultaneous Read and Write
: When one port is writing and the other port is reading from the same location in the memory, the data
written will be valid. However, the read operation would fail and hence the reading port's collision flag is asserted.
The alert flag (COL
x
) is asserted on the 3rd (for both pipe-lined and flow-through output mode) rising clock edge of the affected port
following the collision, and remains low for one cycle. On continuous collisions (one or both ports writing during each access), the collision
alert flag will be asserted and de-asserted every alternate cycle.
Collision detection truth table
[1,2,4,5]
Notes:
1. L = low, H = high, X = don't care
2. Chip Selected (CE0 = L and CE1 =H). True for both ports. Collision flag is not affected if any one or both ports are deselected.
3. “MATCH” indicates that internal addresses of both the ports are the same (refer Counter control truth table).
4. Both Collision Flags are De-asserted on power-up.
5. Collision detection feature is not supported in TQFP package.
CLK
A
R/W
A
CLK
B
R/W
B
Port address
[3]
COL
A
COL
B
Function
L to H
H
L to H
H
MATCH
H
H
Both ports reading. Not a valid collision. No
collision flag asserted on either port.
Port A reading, Port B writing. Valid collision.
Collision flag asserted on port A.
Port B reading, Port A writing. Valid collision.
Collision flag asserted on port B.
Both ports writing. Valid collision. Collision
flag asserted on both ports.
No match. No collision flag asserted on either
port.
L to H
H
L to H
L
MATCH
L
H
L to H
L
L to H
H
MATCH
H
L
L to H
L
L to H
L
MATCH
L
L
L to H
L
L to H
H
NO MATCH
H
H
相關PDF資料 |
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| AS9C25256M2018L-200FC | TERM. F/O CABLE SC-SC/ DPLX/RISER/3M/RED |
| ASCELL3911 | ER 6C 6#16 SKT RECP LINE |
| ASCELL3912 | ER 10C 10#16 SKT RECP LINE |
| ASD07H-12D12 | Isolated and Regulated 7 WATT Open Frame DC/DC Converter |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS9C25512M2018L-200FI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-200TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-200TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-250BC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-250BI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
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