參數(shù)資料
型號： AS9C25256M2018L-166TI
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： TERM. F/O CABLE SC-SC/ DPLX/RISER/1M/BLUE
中文描述： 256K X 18 DUAL-PORT SRAM, 10 ns, PQFP144
封裝： TQFP-144
文件頁數(shù)： 16/30頁
文件大?。?/td> 1100K
代理商： AS9C25256M2018L-166TI
AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 16 of 30
Mailbox Interrupts
The AS9C25512M2018L/AS9C25256M2018L has an Inbuilt Mailbox Logic that can be used for communication between the two ports.
One memory location is assigned as mail box (message center) for each port. The location 7FFFE (HEX) is assigned as the message center
for Port A and 7FFFF (HEX) for Port B (3FFFE and 3FFFF for AS9C25256M2018L). The port A interrupt flag (INT
A
) is asserted when the
port B writes to memory location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). The port A clears the interrupt flag by reading the
address location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). Likewise, the port B interrupt flag (INT
B
) is asserted when the port A
writes to memory location 7FFFF (HEX) (3FFFF for AS9C25256M2018L) and to clear the interrupt flag (INT
B
), the port B must read the
memory location 7FFFF (3FFFF for AS9C25256M2018L).(Refer Interrupt Logic Truth Table).
The interrupt flag is asserted in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-
through mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without de-asserting the
interrupt and each port can write to its own mailbox without asserting the interrupt. If an application does not require message passing, INT
pins can be ignored.
Interrupt logic truth table
[1,4,5]
Notes:
1. L = low, H = high, X = don't care
2. CE
x
is an internal signal ('x' = 'A' or 'B'). CE
x
= H implies 'Chip is Deselected' (CE0
x
= H or CE1
x
=L), CE
x
= L implies 'Chip is Selected' (CE0
x
= L and CE1
x
=H)
3. Address specified here is the internal address (refer Counter control truth table).
4. Both Interrupt Flags are De-asserted on power-up.
5. Interrupt feature is not supported in TQFP package.
6. Address A18 is a NC for AS9C25256M2018L, hence Interrupt addresses are 3FFFF and 3FFFE
CLK
A
R/W
A
CE
A[2]
L to H
L
L to H
X
L to H
X
L to H
H
A18
A
-A0
A[3,6]
7FFFF
X
X
7FFFE
CLK
B
R/W
B
CE
B[2]
A18
B
-A0
B[3,6]
L to H
X
X
L to H
H
L
L to H
L
L
L to H
X
X
INT
A
X
X
L
H
INT
B
L
H
X
X
Function
L
X
X
L
X
Assert Port B Interrupt Flag
De-assert Port B Interrupt Flag
Assert Port A Interrupt Flag
De-assert Port A Interrupt Flag
7FFFF
7FFFE
X
相關(guān)PDF資料
PDF描述
AS9C25512M2018L-200BC TERM. F/O CABLE SC-SC/ DPLX/RISER/2M/BLUE
AS9C25256M2018L-200BC TERM. F/O CABLE SC-SC/ DPLX/RISER/3M/BLUE
AS9C25512M2018L-200BI TERM. F/O CABLE SC-SC/ DPLX/RISER/5M/BLUE
AS9C25256M2018L-200BI TERM. F/O CABLE SC-SC/ DPLX/RISER/10M/BLUE
AS9C25512M2018L-200FC TERM. F/O CABLE SC-SC/ DPLX/RISER/2M/RED
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS9C25256M2018L-200BC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-200BI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-200FC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-200FI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-200TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
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