參數(shù)資料
型號(hào)： AS9C25256M2018L-166FI
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： TERM. F/O CABLE ST-SC/ DPLX/RISER/1M/ORANGE
中文描述： 256K X 18 DUAL-PORT SRAM, 10 ns, PBGA208
封裝： FBGA-208
文件頁(yè)數(shù)： 20/30頁(yè)
文件大?。?/td> 1100K
代理商： AS9C25256M2018L-166FI
AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 20 of 30
Depth and Width expansion
AS9C25512M2018L/AS9C25256M2018L has two chipselects (one active high and other active low) for simple depth expansion. This
permits easy upgrade from 512/256K depth to 1M/512K depth without extra logic. Two such parts can also be combined to obtain an
expanded width of 36 bits or wider.
DQ<0:35>
Notes:
1. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L
2. A<0:19> for AS9C25512M2018L, A<0:18> for AS9C25256M2018L
3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L
Timing waveform of multi device read
[4,5,6]
Notes:
1. Parameters t
CYC
, t
CH
and t
CL
are different in Flow-through and Pipeline mode of operation (Refer AC Timing characteristics).
2. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L
3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L
4. Refer to the above block diagram for the assumed setup.
5. One Bank is assumed to have two AS9C25512M2018L/AS9C25256M2018Ls combined to have an expanded width of 36 bits. Two such Banks are used for depth expansion.
6. All BEn's = L, Counter set in “Load” mode (ADS = L, INC = X, RPT = H), OE =L.
RPT
INC
ADS
OE
BE<0:1>
R/W
CLK
CE1
CE0
RPT
INC
ADS
OE
BE<0:1>
R/W
CLK
CE1
CE0
A
[
D
A
[
D
A
[
A
[
D
D
A
[
A
[
D
D
A
[
A
[
Clock
Clock
Data
Address
Controller
Microprocessor
BANK 1
BANK 0
512/256K
x18
DPSRAM
DPSRAM
A<0:19>
[2]
512/256K
x18
t
CH
t
CL
t
CYC[1]
CLK
R/W
A[19]
[3]
DATA OUT [0:35]
(BANK 0)
[Pipeline Mode]
(BANK 1)
[Pipeline Mode]
DATA OUT [0:35]
A[0:18]
[2]
[Flow-through Mode]
DATA OUT [0:35]
(BANK 1)
(BANK 0)
[Flow-through Mode]
DATA OUT [0:35]
t
AS
t
AH
t
WS
t
WH
A1
A2
A3
A4
A5
A6
A7
A8
t
CDP
t
OHP
t
HZCP
t
LZCP
Q1
Q2
Q4
Q3
t
CDP
t
OHP
t
HZCP
t
LZCP
t
CDF
t
OHF
t
HZCF
t
LZCF
Q4
Q1
Q2
Q3
t
CDF
t
OHF
t
HZCF
Q5
Q6
Read
(Bank0)
(Bank0)
Read
(Bank1)
Read
Read
(Bank0)
Read
(Bank1)
Read
(Bank1)
Read
(Bank0)
t
LZCF
Q5
Q6
Don’t care
Undefined
相關(guān)PDF資料
PDF描述
AS9C25512M2018L-166TC TERM. F/O CABLE ST-SC/ DPLX/RISER/2M/ORANGE
AS9C25256M2018L-166TC TERM. F/O CABLE ST-SC/ DPLX/RISER/3M/ORANGE
AS9C25512M2018L-166TI TERM. F/O CABLE ST-SC/ DPLX/RISER/10M/ORANGE
AS9C25256M2018L-166TI TERM. F/O CABLE SC-SC/ DPLX/RISER/1M/BLUE
AS9C25512M2018L-200BC TERM. F/O CABLE SC-SC/ DPLX/RISER/2M/BLUE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS9C25256M2018L-166TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-166TI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-200BC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-200BI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-200FC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
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