參數(shù)資料
型號(hào)： AS8501-ASOU
廠商： ams
文件頁(yè)數(shù)： 39/41頁(yè)
文件大?。?/td> 0K
描述： IC DATA ACQ 16-SOIC
特色產(chǎn)品： AS8501 High Precision Data Acquisition Ics
標(biāo)準(zhǔn)包裝： 46
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
輸入類型： 模擬，數(shù)字
輸出類型： 模擬，數(shù)字
接口： 串行
電流 - 電源： 5mA
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
產(chǎn)品目錄頁(yè)面： 803 (CN2011-ZH PDF)
AS8501 - Data Sheet
austriamicrosystems
Revision 1.1, 04-April-06
www.austriamicrosystems.com
Page 6 of 40
Electrical characteristics (continued)
VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
symbol
parameter
conditions
min
typ
max
units
cal_err
calibration error
for 30 000 digits output at
full range
G1, 720 mV
G6, 120 mV
G24, 30 mV
G50, 15 mV
G100, 7.5 mV
0.1
0.2
%
1)
lin_err
nonlinearity
gain 6 @ room temp
0.1
0.3
% or 30 digits 2)
gain 24 @ room temp
0.03
0.05
% or 10 digits 2)
gain 50 @ room temp
0.05
0.07
% or 15 digits 2)
gain 100 @ room temp
0.05
0.1
% or 20 digits 2)
lin_errTC
TC of linearity error
all gains
1
5
ppm/K
3)
Vos
offset voltage:
RSHH_RSHL
-40 to 125°C
-0.5
0.2
0.5
V
4)
offset voltage: ETS, ETR,
VBAT
-40 to 85°C
-2
0.5
1
V
4)
85 to 125°C
-4
1
2
V
4)
dVos/dT
Offset voltage drift: RSHH-
RSHL
-40 to 85 °C
0.002
V/K
Ib
input bias/leakage current,
all channels
room temperature
-1
0.2
1
nA
5)
Vndin
voltage noise density
(G=24)
f=0 to 1 kHz
35
50
nV//Hz
6)
Indin
current noise density
(G=24)
f=10 Hz
5
20
100
fA//Hz
6)
en p_p
voltage noise, peak (G=24)
0 to 100 Hz
2
3
5
V
6)
0 to 10 Hz
0.5
1
1.5
V
6)
en_RMS
voltage noise, RMS (G=24) 1000 Hz
1.5
2
V
SNR
signal to noise (G=24,
G4.8)
room temperature
90
100
dBmin
SDR
signal to distortion (G24,
G4.8)
room temperature
80
100
dBmin
CCI
chanel to chanel insulation
room temperature
-70
-90
dBmax
PSRR
power supply rejection ratio 4.9 to 5.1 V
-50
-60
dBmax
Notes:
1)
at room temperature / corresponding calibration factors are stored within the ZZR-register
2
) whatever is lower. Maximum limits for gains 50 and 100 are derived from device characterization and are not tested.
3)
this value measured in raw mode at room temperature and at 60°C. Maximum limits over temperature range are derived from device characterization.
4)
TC variations are included in the above given maximum limit of linearity error. Max value is derived from device characterization and not tested
5)
Leakage current is specified for all gain settings (except G1) for positive input voltages below 200 mV. Test is done at different input voltages with
subsequent extrapolation for 200mV. In the temperature range 85-125°C it may be as high as 5 nA at the upper limit. In normal operation a
temperature independent digital offset of -0.7 digits is present due to internal rounding.
6)
This parameter is not measured directly. It is measured indirectly via gain measurement of the whole path at room temperature
ams
AG
Technical
content
still
valid
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