參數(shù)資料
型號: AS8501-ASOU
廠商: ams
文件頁數(shù): 20/41頁
文件大小: 0K
描述: IC DATA ACQ 16-SOIC
特色產品: AS8501 High Precision Data Acquisition Ics
標準包裝: 46
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
輸入類型: 模擬,數(shù)字
輸出類型: 模擬,數(shù)字
接口: 串行
電流 - 電源: 5mA
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 16-SOIC
包裝: 管件
產品目錄頁面: 803 (CN2011-ZH PDF)
AS8501 - Data Sheet
austriamicrosystems
Revision 1.1, 04-April-06
www.austriamicrosystems.com
Page 26 of 40
The determination of Tcnv and Tres from the parameter settings is:
Tcnv
% R1/(fovs*2)
Tres = MM*Tcnv*R2*2
with R1=OSR and R2=number of averages
8.3
SDI bus operation
SDI bus is a 2-line bi-directional interface between one master and one slave unit. Typically the master unit is a microcontroller with software-
implemented SDI protocol. The ASSP is always the slave unit. SDI bus operation is presented on Figure 10.
During data transfers the sdat signal changes while sclk is low. The sdat signal can change while sclk is high only to generate start or
exception conditions.
Strobe ASSP
The master unit always generates the sclk signal.
The master unit generates the sdat signal in start, direction, address, master-write data and exception conditions. The master sdat pin is in
high-impedance state in master-read data condition.
The slave unit drives the sdat signal only in master-read data condition. In all other cases the slave sdat pin is in high-impedance state. During
data transfer in read condition the internal AD-conversion in continuing but the data in the MSR-register is not updated and the output of the
INTN
Tres
Tcnv
start measurement i
i-1
i+1
i-2
i-1
i
available
results on SDI
SDAT
sclk
Start
Direction
Data transfer
Address
Register data
Exception
Figure 9: INTN pin in modes 1 and 2
Figure 10: SDI bus operation
ams
AG
Technical
content
still
valid
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