參數(shù)資料
型號: AS7C4096-20TIN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 5V/3.3V 512K X8 CMOS SRAM
中文描述: 512K X 8 STANDARD SRAM, 20 ns, PDSO44
封裝: LEAD FREE, TSOP2-44
文件頁數(shù): 6/9頁
文件大?。?/td> 246K
代理商: AS7C4096-20TIN
AS7C4096
AS7C34096
1/13/05; v.1.9
Alliance Semiconductor
P. 6 of 9
AC test conditions
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figures A, B, and C.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 CE or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.
11
All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
350
C
13
320
D
OUT
GND
+3.3V
Figure C: 3.3V Output load
168
Thevenin equivalent:
D
OUT
+1.728V
255
C
13
480
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
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