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參數(shù)資料
| 型號： | AS7C3513B-20TIN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 32K x 16 CMOS SRAM |
| 中文描述： | 32K X 16 STANDARD SRAM, 20 ns, PDSO44 |
| 封裝： | 18.40 X 10.20 MM, LEAD FREE, TSOP2-44 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 217K |
| 代理商： | AS7C3513B-20TIN |
AS7C3513B
3/24/04, v.1.2
Alliance Semiconductor
P. 7 of 10
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 Not applicable.
11
All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A and B.
These parameters are specified with C
L
= 5pF, as in Figure B. Transition is measured
±
500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
350
C
13
320
D
out
GND
+3.3V
Figure B: 3.3V Output load
168
Thevenin equivalent:
D
out
+1.728V
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
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