參數(shù)資料
型號: AS7C34098A-20TI
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3 V 256 K x 16 CMOS SRAM
中文描述: 256K X 16 STANDARD SRAM, 20 ns, PDSO44
封裝: TSOP2-44
文件頁數(shù): 7/10頁
文件大?。?/td> 151K
代理商: AS7C34098A-20TI
AS7C34098A
8/17/04,v. 2.1
Alliance Semiconductor
P. 7 of 10
Write waveform 3
10
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 All write cycle timings are referenced from the last valid address to the first transitioning address.
11
C=30pF, except on High Z and Low Z parameters, where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A and B.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
WZ
t
AH
t
WR
Data
OUT
Data undefined
High Z
High Z
t
AS
t
AW
Data valid
10%
90%
10%
90%
GND
+3.0V
2 ns
Figure A: Input pulse
350
C
11
320
D
OUT
GND
+3.3V
Figure B: 3.3V Output load
168
D
OUT
+1.728V
Thevenin equivalent:
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