參數(shù)資料
型號: AS7C34098A-20TI
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3 V 256 K x 16 CMOS SRAM
中文描述: 256K X 16 STANDARD SRAM, 20 ns, PDSO44
封裝: TSOP2-44
文件頁數(shù): 1/10頁
文件大?。?/td> 151K
代理商: AS7C34098A-20TI
August 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C34098A
3.3 V 256 K × 16 CMOS SRAM
8/17/04, v. 2.1
Alliance Semiconductor
P. 1 of 10
Features
Pin compatible with AS7C34098
Industrial and commercial temperature
Organization: 262,144 words × 16 bits
Center power and ground pins
High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
Low power consumption: STANDBY
- 28.8 mW /max CMOS
Individual byte read/write controls
Easy memory expansion with CE, OE inputs
TTL- and CMOS-compatible, three-state I/O
44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
1024 × 256 × 16
Array
(4,194,304)
OE
LB
CE
WE
Column decoder
R
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
V
CC
GND
A
A
A
A
A
A
A
A
Control circuit
I/O1–I/O8
I/O9–I/O16
UB
I/O
buffer
Pin arrangement for SOJ and TSOP 2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O13
GND
V
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
CE
I/O1
I/O2
I/O3
I/O4
V
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
TSOP2
LB
I/O16
I/O14
2
3
4
A2
A4
1
A1
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
42
40
43
A15
UB
A16
44-pin (400 mil) SOJ
Selection guide
–10
10
4
180
170
8
–12
12
5
160
150
8
–15
15
6
140
130
8
–20
20
7
110
100
8
Unit
ns
ns
mA
mA
mA
Maximum address access time
Maximum output enable access time
Maximum operating current
Industrial
Commercial
Maximum CMOS standby current
相關(guān)PDF資料
PDF描述
AS7C34098A-20TIN Octal Buffers/Drivers With 3-State Outputs 20-SO -40 to 85
AS7C34098 5V/3.3V 256K x 16 CMOS SRAM
AS7C4098-15TI High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-PDIP -55 to 125
AS7C4098-15TIN High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-PDIP -55 to 125
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