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參數(shù)資料
| 型號： | AS7C33512PFS16A-133BI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 16 STANDARD SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 20 MM, BGA-119 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 370K |
| 代理商： | AS7C33512PFS16A-133BI |
AS7C33512PFS16A
AS7C33512PFS18A
4/15/02; v.1.5
Alliance Semiconductor
8 of 14
.
Timing characteristics over operating range
Parameter
Symbol
–166
–150
–133
–100
Unit Notes1
Min Max Min Max Min Max Min Max
Clock frequency
fMax
–
166
–
150
–
133
–
100 MHz
Cycle time (pipelined mode)
tCYC
6
–
6.6
–
7.5
–
10
–
ns
Cycle time (flow-through mode)
tCYCF
10
–10–12
–12–
ns
Clock access time (pipelined mode)- 3.3V VDDQ
tCD 3.3V
-
3.5
-
3.8
-
4.0
-
5.0
ns
Clock access time (pipelined mode)- 2.5V VDDQ
tCD 2.5V
-
4.0
-
4.3
-
4.5
-
5.0
ns
Clock access time (flow-through mode)
tCDF
–
9
–10–10
–12
ns
Output enable LOW to data valid
tOE
–
3.5
–3.8
–4.0
–5.0
ns
Clock HIGH to output Low Z
tLZC
0
–
0
–
0
–
0
–
ns
2,3,4
Data output invalid from clock HIGH
tOH
1.5
–
1.5
–
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
tLZOE
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
tHZOE
–
3.5
–
3.8
–
4.0
–
4.5
ns
2,3,4
Clock HIGH to output High Z
tHZC
–
3.5
–
3.8
–
4.0
–
5.0
ns
2,3,4
Output enable HIGH to invalid output
tOHOE
0–
0–0
–
0–
ns
Clock HIGH pulse width
tCH
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Clock LOW pulse width
tCL
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Address setup to clock HIGH
tAS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Data setup to clock HIGH
tDS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Write setup to clock HIGH
tWS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,7
Chip select setup to clock HIGH
tCSS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,8
Address hold from clock HIGH
tAH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
tDH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
tWH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
tCSH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock HIGH
tADVS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSP setup to clock HIGH
tADSPS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSC setup to clock HIGH
tADSCS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADV hold from clock HIGH
tADVH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold from clock HIGH
tADSPH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock HIGH
tADSCH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
1
See “Notes on page 12.
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| AS7C33512PFS18A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
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