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參數(shù)資料
| 型號(hào)： | AS7C33512PFD18A-166TQIN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| 中文描述： | 512K X 18 STANDARD SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大?。?/td> | 515K |
| 代理商： | AS7C33512PFD18A-166TQIN |
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AS7C33512PFD18A
12/1/04;
v.1.3
Alliance Semiconductor
10 of 20
Timing characteristics for 3.3 V I/O operation
Parameter
Symbol
–166
–133
Unit
Notes
1
Min
Max
Min
Max
Clock frequency
f
Max
t
CYC
–
166
–
133
MHz
Cycle time
Clock access time
6
-
–
7.5
-
–
ns
ns
t
CD
3.5
4.0
Output enable low to data valid
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–
3.5
–
4.0
ns
Clock high to output low Z
0
–
0
–
ns
2,3,4
Data output invalid from clock high
Output enable low to output low Z
1.5
0
–
–
1.5
0
–
–
ns
ns
2
2,3,4
Output enable high to output high Z
–
3.5
–
4.0
ns
2,3,4
Clock high to output high Z
Output enable high to invalid output
–
0
3.5
–
–
0
4.0
–
ns
ns
2,3,4
Clock high pulse width
2.4
–
2.5
–
ns
5
Clock low pulse width
Address setup to clock high
2.3
1.5
–
–
2.5
1.5
–
–
ns
ns
5
6
Data setup to clock high
1.5
–
1.5
–
ns
6
Write setup to clock high
Chip select setup to clock high
1.5
1.5
–
–
1.5
1.5
–
–
ns
ns
6,7
6,8
Address hold from clock high
0.5
–
0.5
–
ns
6
Data hold from clock high
Write hold from clock high
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
6
6,7
Chip select hold from clock high
0.5
–
0.5
–
ns
6,8
ADV setup to clock high
ADSP setup to clock high
1.5
1.5
–
–
1.5
1.5
–
–
ns
ns
6
6
ADSC setup to clock high
1.5
–
1.5
–
ns
6
ADV hold from clock high
ADSP hold from clock high
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
6
6
ADSC hold from clock high
0.5
–
0.5
–
ns
6
1
See “Notes” on page 17
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33512PFD18A | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFD18A-133TQC | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFD18A-133TQCN | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFD18A-133TQI | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFD18A-133TQIN | 3.3V 512K x 18 pipeline burst synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512PFD32A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFD32A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFD32A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFD32A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFD32A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
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