參數(shù)資料
型號(hào)： AS7C33512PFD18A-133TQCN
廠(chǎng)商： ALLIANCE SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 3.3V 512K x 18 pipeline burst synchronous SRAM
中文描述： 512K X 18 STANDARD SRAM, 4.5 ns, PQFP100
封裝： 14 X 20 MM, LEAD FREE, TQFP-100
文件頁(yè)數(shù)： 5/20頁(yè)
文件大小： 515K
代理商： AS7C33512PFD18A-133TQCN
AS7C33512PFD18A
12/1/04;
v.1.3
Alliance Semiconductor
5 of 20
Signal descriptions
Signal
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
I/O
Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE, ZZ,
LBO
are synchronous to this clock.
A,A0,A1
DQ[a,b]
I
SYNC
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
I/O
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
ADSP
I
SYNC
ADSC
I
SYNC
Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
ADV
I
SYNC
Burst advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]
control write enable.
GWE
I
SYNC
BWE
I
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.
BW[a,b]
I
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
OE
I
ASYNC
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally pulled
High.
ZZ
NC
I
-
ASYNC
-
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
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PDF描述
AS7C33512PFD18A-133TQI 3.3V 512K x 18 pipeline burst synchronous SRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS7C33512PFD18A-133TQI 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM
AS7C33512PFD18A-133TQIN 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM
AS7C33512PFD18A-166TQC 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM
AS7C33512PFD18A-166TQCN 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM
AS7C33512PFD18A-166TQI 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM
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