- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381343 > AS7C33512NTD18A-166TQC (ALLIANCE SEMICONDUCTOR CORP) 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD PDF資料下載
參數(shù)資料
| 型號： | AS7C33512NTD18A-166TQC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| 中文描述： | 512K X 18 ZBT SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 439K |
| 代理商： | AS7C33512NTD18A-166TQC |
AS7C33512NTD18A
11/30/04;
v.2.1
Alliance Semiconductor
5 of 19
Signal descriptions
Signal
CLK
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The
duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all
inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not
guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid
pending operations are completed. Similarly, when exiting SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle
should be given while the SRAM is transitioning out of SNOOZE MODE.
I/O
I
Properties
CLOCK
Description
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN
I
SYNC
Clock enable. When de-asserted HIGH, the clock input signal is masked.
A, A0, A1
DQ[a,b]
I
SYNC
SYNC
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
I/O
CE0, CE1,
CE2
I
SYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is HIGH.
ADV/LD
I
SYNC
Advance or Load. When sampled HIGH, the internal burst address counter will increment
in the order defined by the LBO input value. (refer to table on page 2) When LOW, a new
address is loaded.
R/W
I
SYNC
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a
WRITE operation. Is ignored when ADV/LD is HIGH.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
BW[a,b]
I
SYNC
OE
I
ASYNC
Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally pulled
High.
Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.
ZZ
I
ASYNC
NC
-
-
No connects. Note that pin 84 will be used for future address expansion to 18Mb density.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33512NTD18A-166TQCN | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQI | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQIN | 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQC | 3.3V 512K x 32/36 Pipelined SRAM with NTD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512NTD18A-166TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD32A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
| AS7C33512NTD32A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 Pipelined SRAM with NTD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。