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參數(shù)資料
| 型號(hào)： | AS7C33512FT18A-10TQC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 3.3V 512K x 18 Flow-through synchronous SRAM |
| 中文描述： | 512K X 18 STANDARD SRAM, 10 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 10/19頁(yè) |
| 文件大?。?/td> | 506K |
| 代理商： | AS7C33512FT18A-10TQC |
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AS7C33512FT18A
11/30/04, v 1.1
Alliance Semiconductor
10 of 19
Timing characteristics over operating range
Snooze Mode Electrical Characteristics
Parameter
Sym
–75
–85
–10
Unit
Notes
1
1
See “Notes” on page 16.
Min
Max
Min
Max
Min
Max
Cycle time
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
8.5
–
10
–
12
–
ns
Clock access time
–
7.5
–
8.5
–
10
ns
Output enable low to data valid
–
3.5
–
4.0
–
4.0
ns
Clock high to output low Z
2.5
–
2.5
–
2.5
–
ns
2,3,4
Data output invalid from clock high
2.5
–
2.5
–
2.5
–
ns
2
Output enable low to output low Z
0
–
0
–
0
–
ns
2,3,4
Output enable high to output high Z
-
3.5
–
4.0
–
4.0
ns
2,3,4
Clock high to output high Z
-
4.0
–
5.0
–
5.0
ns
2,3,4
Output enable high to invalid output
0
–
0
–
0
–
ns
Clock high pulse width
2.5
–
3.0
–
3.0
–
ns
5
Clock low pulse width
2.5
–
3.0
–
3.0
–
ns
5
Address setup to clock high
2.0
–
2.0
–
2.0
–
ns
6
Data setup to clock high
2.0
–
2.0
–
2.0
–
ns
6
Write setup to clock high
2.0
–
2.0
–
2.0
–
ns
6,7
Chip select setup to clock high
2.0
–
2.0
–
2.0
–
ns
6,8
Address hold from clock high
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock high
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock high
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock high
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock high
2.0
–
2.0
–
2.0
–
ns
6
ADSP setup to clock high
2.0
–
2.0
–
2.0
–
ns
6
ADSC setup to clock high
2.0
–
2.0
–
2.0
–
ns
6
ADV hold from clock high
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold from clock high
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock high
0.5
–
0.5
–
0.5
–
ns
6
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
30
Units
mA
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33512FT18A-10TQCN | 3.3V 512K x 18 Flow-through synchronous SRAM |
| AS7C33512FT18A-10TQI | 3.3V 512K x 18 Flow-through synchronous SRAM |
| AS7C33512FT18A-10TQIN | 3.3V 512K x 18 Flow-through synchronous SRAM |
| AS7C33512FT18A-75TQC | 3.3V 512K x 18 Flow-through synchronous SRAM |
| AS7C33512FT18A-75TQCN | 3.3V 512K x 18 Flow-through synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512FT18A-10TQCN | 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Flow-through synchronous SRAM |
| AS7C33512FT18A-10TQI | 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Flow-through synchronous SRAM |
| AS7C33512FT18A-10TQIN | 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Flow-through synchronous SRAM |
| AS7C33512FT18A-75TQC | 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Flow-through synchronous SRAM |
| AS7C33512FT18A-75TQCN | 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Flow-through synchronous SRAM |
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