參數(shù)資料
型號: AS7C332MNTD18A-166TQIN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 2M x 18 Pipelined SRAM with NTD
中文描述: 2M X 18 ZBT SRAM, 3.5 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁數(shù): 15/18頁
文件大?。?/td> 439K
代理商: AS7C332MNTD18A-166TQIN
12/23/04, V 1.6
Alliance Semiconductor
P. 15 of 18
AS7C332MNTD18A
AC test conditions
Output load: For t
LZC
, t
LZOE
, t
HZOE
, and t
HZC
, see Figure C. For all others, see Figure B.
Notes
1) For test conditions, see “AC test conditions”, Figures A, B, and C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
HZOE
is less than t
LZOE
, and t
HZC
is less than t
LZC
at any given temperature and voltage.
5) t
CH
is measured high above V
IH
, and t
CL
is measured low below V
IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to
R/
W
and
BW[a,b]
.
8) Chip select refers to
CE0
,
CE1, and CE2
.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+
3.0V
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
353
/1538
5 pF*
319
/1667
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
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