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參數(shù)資料
| 型號： | AS7C331MNTD32A-167TQCN |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | SRAM |
| 英文描述： | 1M X 32 ZBT SRAM, 7.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 454K |
| 代理商： | AS7C331MNTD32A-167TQCN |
4/26/04, V 1.2
Alliance Semiconductor
P. 5 of 22
AS7C331MNTD32A
AS7C331MNTD36A
Signal descriptions
Signal
I/O
Properties Description
CLK
I
CLOCK
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
CEN
I
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1
I
SYNC
Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b,c,d]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2
I
SYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
ADV/LD
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
R/W
I
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
BW[a,b,c,d]
I
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE
I
ASYNC
Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
ISTATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
FT
ISTATIC
Selects Pipeline or Flow-through mode. When tied to VDD or left floating, enables Pipeline mode.
When driven Low, enables single register Flow-through mode. This signal is internally pulled High.
TDO
O
SYNC
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA
only)
TDI
I
SYNC
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)
TMS
I
SYNC
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA only)
TCK
O
SYNC
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA
only)
ZZ
I
ASYNC
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
No connects.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C331MNTD32A-200TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1M x 32/36 Pipelined SRAM with NTD |
| AS7C331MNTD32A-200TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1M x 32/36 Pipelined SRAM with NTD |
| AS7C331MNTD32A-200TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1M x 32/36 Pipelined SRAM with NTD |
| AS7C331MNTD32A-200TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1M x 32/36 Pipelined SRAM with NTD |
| AS7C331MNTD36A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1M x 32/36 Pipelined SRAM with NTD |
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