參數(shù)資料
型號(hào): AS7C331MNTD32A-167TQCN
廠商: INTEGRATED SILICON SOLUTION INC
元件分類(lèi): SRAM
英文描述: 1M X 32 ZBT SRAM, 7.5 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁(yè)數(shù): 11/22頁(yè)
文件大小: 454K
代理商: AS7C331MNTD32A-167TQCN
4/26/04, V 1.2
Alliance Semiconductor
P. 19 of 22
AS7C331MNTD32A
AS7C331MNTD36A
AC test conditions
Notes
1) For test conditions, see “AC test conditions”, Figures A, B, and C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
5) tCH is measured high above VIH, and tCL is measured low below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/W and BW[a,b,c,d]
.
8) Chip select refers to CE0, CE1, and CE2.
Output load: For tLZC, tLZOE, tHZOE, and tHZC, see Figure C. For all others, see Figure B.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
DOUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
for 2.5V I/O
Thevenin equivalent:
353
/1538
5 pF*
319
/1667
DOUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
7
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