參數(shù)資料
型號(hào): AS7C33128PFD18B-166TQIN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 128K x 18 pipeline burst synchronous SRAM
中文描述: 128K X 18 STANDARD SRAM, 3.5 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁(yè)數(shù): 16/19頁(yè)
文件大?。?/td> 538K
代理商: AS7C33128PFD18B-166TQIN
AS7C33128PFD18B
1/31/05; v.1.2
Alliance Semiconductor
P. 16 of 19
AC test conditions
Output load: see Figure B, except for t
LZC
, t
LZOE
, t
HZOE
, t
HZC
, see Figure C.
Z
0
= 50
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
V
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
353
/ 1538
5 pF*
319
/ 1667
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
Notes
1
2
3
4
5
6
For test conditions, see
AC Test Conditions
, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
HZOE
is less than t
LZOE
; and t
HZC
is less than t
LZC
at any given temperature and voltage.
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to
GWE
,
BWE
,
BW[a,b].
Chip select refers to
CE0
,
CE1
,
CE2
7
8
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