參數(shù)資料
型號: AS7C33128PFD18B-200TQIN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 128K x 18 pipeline burst synchronous SRAM
中文描述: 128K X 18 STANDARD SRAM, 3 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁數(shù): 1/19頁
文件大?。?/td> 538K
代理商: AS7C33128PFD18B-200TQIN
February 2005
Copyright Alliance Semiconductor. All rights reserved.
AS7C33128PFD18B
3.3V 128K
×
18 pipeline burst synchronous SRAM
1/31/05; v.1.2
Alliance Semiconductor
P. 1 of 19
Features
Organization: 131,072 words × 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.0/3.5/4.0 ns
Fast OE access time: 3.0/3.5/4.0 ns
Fully synchronous register-to-register operation
Double-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Selection guide
–200
–166
–133
Units
Minimum cycle time
Maximum clock frequency
5
6
7.5
133
ns
200
166
MHz
Maximum clock access time
3.0
3.5
4
ns
Maximum operating current
Maximum standby current
375
130
350
100
325
90
mA
mA
Maximum CMOS standby current (DC)
30
30
30
mA
Logic block diagram
Burst logic
ADSP
CLK
LBO
CLK
CS
CLR
17
15
17
A[16:0]
17
Address
D
CS
Q
CLK
128K × 18
Memory
array
18
18
DQb
CLK
D
registers
D
registers
Q
DQa
CLK
Q
Enable
CE
D
Q
Enable
rdelay
CLK
D
Q
Output
registers
CLK
Input
registers
Power
down
2
CE0
BW
b
BW
a
OE
ZZ
OE
CLK
BWE
GWE
18
DQ [a,b]
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