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參數(shù)資料
| 型號： | AS7C256A-10TCN |
| 廠商： | ALLIANCE MEMORY INC |
| 元件分類： | SRAM |
| 英文描述： | IC,AS7C256A-10TCN,TSOP-28 ASY SRAM,10NS,32K X 8,5V |
| 中文描述： | 32K X 8 STANDARD SRAM, 10 ns, PDSO28 |
| 封裝： | 8 X 13.4 MM, LEAD FREE, TSOP1-28 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 248K |
| 代理商： | AS7C256A-10TCN |
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 2 of 9
Functional description
The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including
PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V
operation without sacrificing performance or operating margins.
The device enters standby mode when CE is high. CMOS standby mode consumes
≤11 mW. Normal operation offers 75%
power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns
are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank
memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged
in high volume industry standard packages.
Absolute maximum ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t care, L = Low, H = High
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.5
+7.0
V
Voltage on any pin relative to GND
Vt2
–0.5
VCC + 0.5
V
Power dissipation
PD
–1.0
W
Storage temperature (plastic)
Tstg
–65
+150
oC
Ambient temperature with VCC applied
Tbias
–55
+125
oC
DC current into outputs (low)
IOUT
–20
mA
CE
WE
OE
Data
Mode
H
X
High Z
Standby (ISB, ISB1)
L
H
High Z
Output disable (ICC)
LHL
DOUT
Read (ICC)
LL
X
DIN
Write (ICC)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C256A-10TCNTR | 功能描述:靜態(tài)隨機存取存儲器 256K, 5V, 10ns, FAST 32K x 8 Asynch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| AS7C256A-10TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 32K X 8 CMOS SRAM (Common I/O) |
| AS7C256A-10TIN | 功能描述:靜態(tài)隨機存取存儲器 256K, 5V, 10ns, FAST 32K x 8 Asynch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| AS7C256A-10TINTR | 功能描述:靜態(tài)隨機存取存儲器 256K, 5V, 10ns, FAST 32K x 8 Asynch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| AS7C256A-12JC | 制造商:Alliance Semiconductor Corporation 功能描述:Static RAM, 32Kx8, 28 Pin, Plastic, SOJ |
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