參數(shù)資料
型號: AS7C256A-10JIN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 5V 32K X 8 CMOS SRAM (Common I/O)
中文描述: 32K X 8 STANDARD SRAM, 10 ns, PDSO28
封裝: 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28
文件頁數(shù): 6/9頁
文件大?。?/td> 248K
代理商: AS7C256A-10JIN
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 6 of 9
AC test conditions
- Output load: see Figure B
- Input pulse level: GND to V
CC
See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 C=30pF, except on High Z and Low Z parameters, where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on
CE
is required to meet I
SB
specification.
For test conditions, see
AC Test Conditions
, Figures A, B.
These parameters are specified with CL = 5pF, as in Figures B. Transition is measured
±
500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE
is High for read cycle.
CE
and
OE
are Low for read cycle.
Address valid prior to or coincident with
CE
transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
255
C
10
480
D
out
GND
+5.0V
168
D
out
+1.72V
Figure B: Output load
Thevenin equivalent
10%
90%
10%
90%
GND
V
CC
Figure A: Input pulse
2 ns
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AS7C256A-10TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 32K X 8 CMOS SRAM (Common I/O)
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