參數(shù)資料
型號(hào): AS7C251MNTF36A-75TQI
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2.5V 1M x 32/36 Flowthrough SRAM with NTD
中文描述: 1M X 36 ZBT SRAM, 7.5 ns, PQFP100
封裝: 14 X 20 MM, TQFP-100
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 414K
代理商: AS7C251MNTF36A-75TQI
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 4 of 18
Functional Description
The AS7C251MNTF32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory
(SRAM) organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE Write.
This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
) architecture, featuring an enhanced
write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for one dead cycle for valid data to become available. This dead cycle can significantly reduce overall
bandwidth for applications requiring random access or read-modify-write operations.
NTD
devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow-
through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.
With NTD
, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 36
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write
operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by
any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C251MNTF32A/36A operates with a 2.5V ± 5% power supply for the device core (V
DD
). These devices are
available in 100-pin TQFP package.
TQFP Capacitance
*Guranteed not tested
TQFP thermal resistance
Parameter
Symbol
C
IN*
C
I/O*
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
Input capacitance
I/O capacitance
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)
1
1 This parameter is sampled
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
1–layer
θ
JA
θ
JA
40
°
C/W
4–layer
22
°
C/W
Thermal resistance
(junction to top of case)
1
θ
JC
8
°
C/W
相關(guān)PDF資料
PDF描述
AS7C251MNTF36A-85TQC 2.5V 1M x 32/36 Flowthrough SRAM with NTD
AS7C251MNTF36A-85TQCN 2.5V 1M x 32/36 Flowthrough SRAM with NTD
AS7C251MNTF36A-85TQI 2.5V 1M x 32/36 Flowthrough SRAM with NTD
AS7C251MNTF36A-10TQC DIODE ZENER SINGLE 1000mW 20Vz 12.5mA-Izt 0.05 5uA-Ir 15.2Vr DO41-GLASS 5K/REEL
AS7C251MNTF36A-10TQCN DIODE ZENER SINGLE 1000mW 30Vz 8.5mA-Izt 0.05 5uA-Ir 22.8Vr DO41-GLASS 5K/REEL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS7C251MNTF36A-75TQIN 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 1M x 32/36 Flowthrough SRAM with NTD
AS7C251MNTF36A-85TQC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 1M x 32/36 Flowthrough SRAM with NTD
AS7C251MNTF36A-85TQCN 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 1M x 32/36 Flowthrough SRAM with NTD
AS7C251MNTF36A-85TQI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 1M x 32/36 Flowthrough SRAM with NTD
AS7C251MNTF36A-85TQIN 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 1M x 32/36 Flowthrough SRAM with NTD