參數(shù)資料
型號(hào): AS7C251MFT18A-85TQIN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2.5V 1M x 18 flowthrough burst synchronous SRAM
中文描述: 1M X 18 STANDARD SRAM, 8.5 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁數(shù): 6/19頁
文件大?。?/td> 511K
代理商: AS7C251MFT18A-85TQIN
AS7C251MFT18A
12/24/04, v. 1.2
Alliance Semiconductor
6 of 19
Write enable truth table (per byte)
Key:
X = don’t care; L = low; H = high; B
WE
, B
Wn
= internal write signal
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function
GWE
L
H
H
H
H
H
BWE
X
L
L
L
H
L
BWa
X
L
L
H
X
H
BWb
X
L
H
L
X
H
Write all bytes (a, b)
Write byte a
Write byte b
Read
Operation
ZZ
H
L
L
L
L
OE
X
L
H
X
X
I/O Status
High-Z
Dout
High-Z
Din, High-Z
High-Z
Snooze mode
Read
Write
Deselected
Interleaved burst address (LBO = 1)
A1 A0
0 0
2
nd
Address
0 1
3
rd
Address
1 0
4
th
Address
1 1
Linear burst address (LBO = 0)
A1 A0
0 0
0 1
1 0
1 1
A1 A0
0 1
0 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
1 0
0 1
0 0
A1 A0
0 1
1 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
1
st
Address
1
st
Address
2
nd
Address
3
rd
Address
4
th
Address
相關(guān)PDF資料
PDF描述
AS7C251MFT18A-10TQIN 2.5V 1M x 18 flowthrough burst synchronous SRAM
AS7C251MFT18A-75TQC High Speed CMOS Logic Triple 3-Input AND Gates 14-SOIC -55 to 125
AS7C251MFT18A-75TQCN 2.5V 1M x 18 flowthrough burst synchronous SRAM
AS7C251MFT18A-75TQI High Speed CMOS Logic Triple 3-Input AND Gates 14-SOIC -55 to 125
AS7C251MFT18A 2.5V 1M x 18 flowthrough burst synchronous SRAM
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