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參數(shù)資料
| 型號： | AS4LC8M8S0-10FTC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 566K |
| 代理商： | AS4LC8M8S0-10FTC |
Advance information
Copyright 2000 Alliance Semiconductor. All rights reserved.
AS4LC8M8S0
AS4LC4M16S0
7/5/00
ALLIANCE SEMICONDUCTOR
1
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Features
PC100/133 compliant
Organization
- 2,097,152 words × 8 bits × 4 banks (8M×8)
- 1,048,576 words × 16 bits × 4 banks (4M×16)
Fully synchronous
- All signals referenced to positive edge of clock
Four internal banks controlled by BA0/BA1 (bank select)
High speed
- 133/125/100 MHz
- 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
Low power consumption
- Standby:7.2 mW max, CMOS I/O
4096 refresh cycles, 64 ms refresh interval
Auto refresh and self refresh
Automatic and direct precharge
Burst read, single write operation
Can assert random column address in every cycle
LVTTL compatible I/O
3.3V power supply
JEDEC standard package, pinout and function
- 400 mil, 54-pin TSOP II
Read/write data masking
Programmable burst length (1/2/4/8/full page)
Programmable burst sequence (sequential/interleaved)
Programmable CAS latency (2/3)
Pin arrangement
A3
V
CC
A4
V
SS
V
CC
DQ0
V
CCQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
CCQ
DQ5
DQ6
V
SSQ
DQ7
V
CC
LDQM
WE
CAS
RAS
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
CCQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
5
CS
BA0
BA1
A10
A0
A1
A2
NC
DQ1
V
SSQ
NC
DQ2
V
CCQ
NC
DQ3
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
DQ7
V
SSQ
NC
DQ6
V
CCQ
NC
DQ5
V
SSQ
NC
DQ4
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
4
A3
V
CC
V
CC
DQ0
V
CCQ
A4
V
SS
V
SS
AS4LC4M16S0
AS4LC4M16S0
Pin designation
Pin(s)
Description
DQM (8M×8)
UDQM/LDQM(4M×16)
A0 to A11
BA0, BA1
DQ0 to DQ7 (8M×8)
DQ0 to DQ15 (4M×16)
RAS
CAS
WE
CS
V
CC
, V
CCQ
V
SS
, V
SSQ
CLK
CKE
Output disable/write mask
Address inputs
Bank select inputs
Input/output
Row address strobe
Column address strobe
Write enable
Chip select
Power (3.3V ± 0.3V)
Ground
Clock input
Clock enable
Selection guide
Symbol
f
max
t
AC
t
AC
t
S
t
H
t
RCD
t
RP
-75 (PC133)
133
–
5.4
1.5
0.8
3
3
3/3/3
-8
125
–
6
2
1.0
3
3
3/3/3
-10F (PC100)
100
6
–
2
1.0
2
2
2/2/2
-10 (PC100)
100
–
6
2
1.0
3
3
3/3/3
Unit
MHz
ns
ns
ns
ns
cycles
cycles
Bus frequency
Minimum clock access time
CL = 2
CL = 3
Minimum setup time
Minimum hold time
Minimum RAS to CAS delay
Minimum RAS precharge time
Remarks: (CL/t
RCD
/t
RP
)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4LC8M8S0-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
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| AS4LC8M8S0-8TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
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