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參數(shù)資料
| 型號： | AS3588AQ |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 路由/交換 |
| 英文描述： | AB 7C 7#8 PIN RECP |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 98K |
| 代理商： | AS3588AQ |
Data Sheet
AS3588A
Rev. 3.1
Page 12 of 15
July 1999
Write Timing Characteristics (Figure 6):
Operation over recommended temperature and voltage range
Symbol
Parameter
Condition
Min.
Typ.*
Max.
Units
tWLWR
Write Pulse Low Width
150
ns
tWHWR
Write Pulse High Width
tCK
ns
tREP
Repetition Interval be-
tween active Write Pulses
High Level Setup Time to
active Read Pulse
High Level Hold Time from
active Read Pulse
tREP=40+2 tCK+tWLCK
+ tRCK
see
ns
formula
tSHRD
0
ns
tHHRD
20
ns
tRWR
Write Pulse Rise Time
60
ns
tFWR
tSLCSWR
Write Pulse Fall Time
CS Low Setup Time to
WR Falling Edge
CS Low Hold time from
WR Rising Edge
CS High Setup Time to
WR Falling Edge
CS High Hold Time from
WR Rising Edge
C/D Setup Time to Write
Pulse End
C/D Hold Time from Write
Pulse End
Address Select Setup Time
to Write Pulse End
Adress Select Hold Time
from Write Pulse End
60
ns
Active State
0
ns
tHLCSWR
Active State
0
ns
tSHCSWR
Inative State
0
ns
tHHCSWR
Inactive State
0
ns
tSCDWR
130
ns
tHCDWR
25
ns
tSASWR
130
ns
tHASWR
25
ns
tWDR
tPDDR
Data Ready Low Time
Data Ready Delay Time
from Write Pulse End
Data Setup Time to Write
PulseEnd
Data Hold Time from Write
Pulse End
Opcodes 5, 6
Opcode 5; CL=50pF
Active Opcode
2 tCK
ns
5 tCK
14 tCK
tSDWR
130
ns
tHDWR
25
ns
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing
Note
: Because of internal clock re-synchronization one single additional requirement is recommended in order to produce a
simultaneous instruction execution in a multi-chip configuration: WR rising edge has to be 20 to 20 + tWL(cK) nsec late relative
to clock falling edge.
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| AS358A | 制造商:BCDSEMI 制造商全稱:BCD Semiconductor Manufacturing Limited 功能描述:LOW POWER DUAL OPERATIONAL AMPLIFIERS |
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