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AS2842/3/4/5
Current Mode Controller
ASTEC Semiconductor
54
latch is still fully operative, and the normal termi-
nation of this cycle by the current sense com-
parator will latch the output low until the over-
temperature condition is rectified. Cycling the
power will reset the over-temperature disable
mechanism, or the chip will re-start after cooling
through a nominal hysteresis band.
Section 2 – Design Considerations
2.1 Leading edge filter
The current sensed by R
S
contains a leading
edge spike as shown in Figure 20. This spike is
caused by parasitic elements within the circuit
including the interwinding capacitance of the
power transformer and the recovery characteris-
tics of the rectifier diode(s). The spike, if not
properly filtered, can cause stability problems by
prematurely terminating the output pulse.
A simple RC filter is used to suppress the spike.
The time constant should be chosen such that
it approximately equals the duration of the spike.
A good choice for R
1
is 1 k
, as this value
is optimum for the filter and at the same
time, it simplifies the determination of R
SLOPE
(Section 2.2). If the duration of the spike is, for
example, 100 ns, then C is determined by:
C
=
=
=
Time Constant
k
ns
k
pF
100
1
(6)
100
1
2.2 Slope compensation
Current-mode controlled converters can experi-
ence instabilities or subharmonic oscillations
when operated at duty ratios greater than 50%.
Two different phenomena can occur as shown
Figure 22.
Slope Compensation
T
0
D
1
D
2
T
1
I
PK
V
E
I
L
2
I
L
1
I
AVG 2
I
AVG 1
m
1
m
2
(a)
T
0
D
1
D
2
T
1
V
E
I
m
1
m
2
(b)
I'
T
0
D
1
D
2
T
1
V
E
I
L
2
I
L
1
I
AVG 1
= I
AVG 2
m
1
m
2
(c)
m = m
2
/2
T
0
D
1
D
2
T
1
I
m
1
M
2
(d)
I'
V
E
m = m
2
/2