參數(shù)資料
型號(hào)： AS2844
廠商： Electronic Theatre Controls, Inc.
英文描述： Current Mode Controller
中文描述： 電流模式控制器
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 94K
代理商： AS2844
ASTEC Semiconductor
Current Mode Controller
AS2842/3/4/5
51
In most typical power supply designs, the
converter’s output voltage is divided down and
monitored at the error amplifier’s inverting input,
V
FB
. A simple resistor divider network is used and
is scaled such that the voltage at V
FB
is 2.5 V
when the converter’s output is at the desired
voltage. The voltage at V
FB
is then compared to
the internal 2.5 V reference and any slight differ-
ence is amplified by the high gain of the error
amplifier. The resulting error amplifier output is
level shifted by two diode drops and is then
divided by three to provide a 0 to 1 V reference
(V
E
) to one input of the current sense compara-
tor. The level shifting reduces the input voltage
range of the current sense input and prevents the
output from going high when the error amplifier
output is forced to its low state. An internal clamp
limits V
E
to 1.0 V. The purpose of the clamp is
discussed in Section 1.5.
1.4.1 Loop compensation
Loop compensation of a power supply is neces-
sary to ensure stability and provide good
line/load regulation and dynamic response.
It is normally provided by a compensation
network connected between the error amplifier’s
output (COMP) and inverting input as shown
in Figure 17. The type of network used depends
on the converter topology and in particular, the
characteristics of the major functional blocks
within the supply - i.e. the error amplifier, the
modulator/switching circuit, and the output filter.
In general, the network is designed such that the
converters overall gain/phase response
approaches that of a single pole with a –20 dB/
decade rolloff, crossing unity gain at the highest
possible frequency (up to f
SW
/4) for good
dynamic response, with adequate phase margin
(> 45
°
) to ensure stability.
Figure 18 shows the Gain/Phase response of the
error amplifier. The unity gain crossing is at
1.2 MHz with approximately 57
°
C of phase
margin. This information is useful in determining
the configuration and characteristics required for
the compensation network.
One of the simplest types of compensation net-
works is shown in Figure 19. An RC network
provides a single pole which is normally set to
compensate for the zero introduced by the the
output capacitor’s ESR. The frequency of the
pole (f
P
) is determined by the formula;
1
2
π
R C
=
(5)
Figure 19.
A Typical Compensation Network
Frequency (Hz)
G
10
2
210
180
150
120
90
60
30
0
–30
–60
240
10
1
10
3
10
4
10
5
10
6
10
7
–20
0
20
40
60
80
P
Gain
Phase
Figure 18.
Gain/Phase Response of the
AS2842
–
E/A
+
2.50 V
To PWM
V
OUT
R
I
R
F
C
F
R
BIAS
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