
AS2702 – AS-Interface Slave IC
Revision 1.3, 21-Aug-08
Page 6 of 13
Data Port Pins D3, …, D0 and Data Strobe Pin DSTBn
Basically data port D3, …, D0 is designed for bidirectional data transfer out of and into the slave device. Each data port pin is
equipped with both a low-side open-drain output stage as well as an input stage to this purpose.
Depending on the so-called IO-configuration code, written and stored in the slave device, each data port pin is individually set to
behave as
output, or
output/input, or
input.
The timing of the data transfer is presented in Figure 3.
Strobe signal DSTBn flags and governs the data transfer as follows:
a)
data port pin is set ‘output’:
output data become valid upon the HL-edge of the strobe and will remain so until the next HL-edge, hence during the entire
strobe cycle;
b)
data port pin is set ‘output/input’:
output data become valid upon the HL-edge of the strobe and will remain so until it’s LH-edge; input data to be valid within a
specific time window relative to the HL-edge, after completion of the strobe’s L-phase;
c)
data port pin is set ‘input’:
input data to be valid within a specific time window relative to the HL-edge of the strobe, after completion of the strobe’s
L-phase.
If necessary, output data as per a) and b) can be easily latched with the LH-edge of strobe DSTBn as they will remain valid for
about 0.4μs beyond as a minimum.
Care must be taken however, that signal delay added by external circuitry is lower for the strobe than for the data.
Data in
Data out
Data in
Data out
t
STB
t
DSTBn
+ 0.4 μs
t
DSTBn
+ t
OUTOFF
t
DSTBn
t
INPmin
t
INPmax
Dx
Dx
DSTBn
Figure 3
Timing of data transfer at data port D3, …, D0 relative to strobe DSTBn
The following table specifies the timing parameters relating to Figure 3:
Symbol
Parameter
tSTB
Delay DSTBn HL-edge to Dx output data valid
tDSTBn
DSTBn strobe width
tOUTOFF
Delay DSTBn LH-edge to Dx output off
tINP
Input data valid time window
Min
6
0.2
10.5
Max
1.5
6.8
1
12.5
Unit
μs
μs
μs
μs
Note
1
2
3