參數(shù)資料
型號: AS2701
廠商: AUSTRIAMICROSYSTEMS AG
英文描述: AS-Interface Slave IC
中文描述: AS - Interface的奴隸集成電路
文件頁數(shù): 5/16頁
文件大?。?/td> 180K
代理商: AS2701
AS-Interface Slave IC
AS2701A (ISA3+)
Rev. C, October 2000
Page 5 of 16
Write Cycle
After the device address, the write cycle R/W-Bit=0, necessary for the identification of the write
cycle, is sent. The E
2
PROM acknowledges the correct receipt with the acknowledge bit ACK.
Then the data byte which should be written into the E
2
PROM reacknowledges with an ACK
signal of the E
2
PROM. The STOP condition ends the cycle.
Read Cycle
The read cycle is similar to the herein described write cycle. In this case the R/W-Bit = 1 which
causes the E
2
PROM to place read data for the received Byte address on the bus after the
acknowledge.
START
Condition
STOP
Condition
SDA
SCL
The
START condition
is recognized by the E
2
PROM when a H/L edge arises on the dataline
SDA during the high phase of the clock.
The
STOP condition
is present when a L/H edge arises on the dataline SDA during the high
phase of the clock SCL. The timing of the E
2
PROM interface is derived from the AS-Interface
quartz frequency of 5.333 MHz.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS2701A 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:AS-Interface Slave IC
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AS2702_1 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:AS-Interface Slave IC