參數(shù)資料
型號: AS2701
廠商: AUSTRIAMICROSYSTEMS AG
英文描述: AS-Interface Slave IC
中文描述: AS - Interface的奴隸集成電路
文件頁數(shù): 4/16頁
文件大?。?/td> 180K
代理商: AS2701
AS-Interface Slave IC
AS2701A (ISA3+)
Rev. C, October 2000
Page 4 of 16
Functional Description
The IC identifies and decodes the supply voltage overlapping signals of the master telegram. If
the slave address contained within the master telegram coincides with the stored information
in the E
2
PROM of the slave address, the corresponding master command of the addressed
AS-Interface slave IC is executed.
After decoding of the master telegram the addressed AS-Interface slave IC responds with a
corresponding slave answer on the AS-Interface line.
The AS-Interface slave IC extracts its own supply voltage and the supply voltage for the
E
2
PROM from the AS-Interface line. At the same time, the IC provides a direct voltage for the
peripheral UOUT which results from U
LTGP
-U
DROP
for a maximum current of 35 mA.
The receive block detects the signal on the AS-Interface wire LTGP. The reference voltages of
the signal comparators are (52.5 ± 5) % of the maximum signal value and are controlled by a
peak value detector in the following mode: The comparator level is set to its default value by
Reset or if a non-correct signal is received.
If a line pause is detected, the level reset is released and the IC is able to adapt itself to
different signal levels. If the IC is not synchronized yet, the level adaption is faster (smaller
attack and decay time constants) as in the synchronous case.
The output information of the receive blocks are the signals: "imp_pos" and "imp_neg".
The transmit block drives the output level for the modulated transmit signal edges. The
transmit block consists of the NMOS transistor (transmit transistor), DAC for transmit signal
formation and a Jabber-Inhibit Circuitry. The DAC is addressed by the digital block. If the
transmitter is active more than typ. 300μs the Jabber-Inhibit circuit separates the IC from the
AS-Interface line. This condition can only be left by a Power-On-Reset.
In the digital block the received signal is analyzed, the transmit signal is generated and the
data and parameter ports as well as the E
2
PROM interface are driven. The E
2
PROM interface
acts as a serial two-wire interface with the following transmission streams:
After the AS-Interface slave IC has sent the START condition, the device address is
transmitted. This address would allow the selection of a maximum of 8 possible E
2
PROM ICs,
is however fixed to 000 by the AS-Interface slave IC. Therefore in the application pins AO...A2
of the E
2
PROM are connected to Uss.
Device-Address
A
1
1
0
0
A2
A1
A0
1
R
Data
A
P
S
SDA
S
1
1
0
0
A2
A1
A0
0
Device-Address
Byte-Address
A
R
Byte Read Cycle
A
SDA
S
1
1
0
0
A2
A1
A0
0
Device-Address
Byte-Address
A
R
Byte Write Cycle
Data
A
A
P
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相關代理商/技術參數(shù)
參數(shù)描述
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