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| 型號(hào)： | AS1527-BSOT |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | ADC |
| 英文描述： | 10-bit ADC, 1-Channel, 73ksps; Package Type: SOIC-8 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 751K |
| 代理商： | AS1527-BSOT |
www.austriamicrosystems.com
Revision 1.03
12 - 21
AS1526/AS1527
Data Sheet
- Detailed Description
The devices’ input tracking circuitry has a 2.5MHz small-signal bandwidth, thus it is possible to under-sample (digitize
high-speed transient events) and measure periodic signals with bandwidths exceeding the devices’ sampling rate.
Note:
Anti-aliasing filtering should be used to avoid aliasing of unwanted high-frequency signals into the bandwidth of
interest.
Input Protection
Internal protection diodes clamp the analog input to V
DD
and GND, allowing the input to swing from (GND - 0.3V) to
(V
DD
+ 0.3V) without damage. However, for accurate conversions near full scale, the input must not exceed V
DD
by
more than 50mV, or be lower than GND by 50mV.
Note:
If the analog input exceeds the supply by 50mV, limit the input current to 2mA.
Track/Hold
In track mode, the analog signal is acquired and stored in the internal hold capacitors. During acquisition, the analog
input at pin AIN charges capacitor C
HOLD
(see Figure 24 on page 11)
. Bringing CSN low ends the acquisition interval
and the charge on C
HOLD
represent the sampled input voltage.
In hold mode, the T/H switches are opened thus the input is disconnected from the capacitor C
HOLD.
During this mode
the successive approximation is performed which in turn forms a digital representation of the analog input signal. At the
end of the conversion, the input side of the in meantime discharged C
HOLD
switches back to AIN, and C
HOLD
charges
to the input signal again.
The maximum time for the T/H to acquire a signal (t
ACQ
) is a function of how quickly its input capacitance is charged.
t
ACQ
increases proportionally to the input signal’s impedance, and at higher impedances more time must be allowed
between conversions. t
ACQ
is also the minimum time needed for the signal to be acquired, and is calculated by:
t
ACQ
= 7(R
S
+ R
IN
) x 21pF
Where:
R
IN
= 4.5k
Ω
R
S
= the input signal’s source impedance.
t
ACQ
is never less than 1.5μs. Source impedances < 1k
Ω
do not significantly affect the AC performance of the devices.
(EQ 1)
Note:
Higher source impedances can be used if a 0.01μF capacitor is connected to the analog input. Note that the
input capacitor forms an RC filter with the input source impedance, limiting the devices’ input signal bandwidth.
External Clock
The AS1526/AS1527 do not require an external clock for analog-to-digital data conversion. This allows the micropro-
cessor to read back the conversion results at any clock rate from up to 2.1MHz at any time. The clock duty cycle is
unrestricted if each clock phase is at least 200ns.
Note:
The external clock must not be run while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled by digital inputs CSN and SCLK. Refer to Figures
25
-
27
(see page 13
) for graphical timing and control information.
The falling edge on pin CSN initiates a conversion sequence:
1. The T/H stage holds the voltage at pin AIN, and the A/D conversion begins.
2. Pin DOUT changes from high-impedance to logic-low. SCLK must be kept low during the conversion.
3. The internal SAR stores the data during the conversion process.
4. Pin DOUT going high indicates the conversion process has completed.
5. The rising edge of pin DOUT can be used as a framing signal.
6. SCLK shifts the data out of this register any time after the conversion is complete.
7. DOUT transitions on the falling edge of pin SCLK.
8. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since
there are 10 data bits and one leading high-bit or 10 data bits, two sub bits, and one leading high-bit, at least 11 or
13 falling clock edges are needed to shift out these bits, respectively.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS1527BSOU | 制造商:AMS 功能描述:IC ADC 10BIT 73KSPS SOIC-8 制造商:AMS 功能描述:IC, ADC, 10BIT, 73KSPS, SOIC-8; Resolution (Bits):10bit; Sampling Rate:73kSPS; Supply Voltage Type:Single; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Supply Current:1.4mA; Digital IC Case Style:SOIC; No. of Pins:8; DNL:1LSB ;RoHS Compliant: Yes |
| AS1527-BSOU | 功能描述:IC A/D 10-BIT 1-CH 73K 8-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AS1528 | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:Micro-Power, 10-Bit, 150ksps, ADC, Single Ended or Differential |
| AS1528_1 | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:Micro-Power, 10-Bit, 150ksps, ADC, Single Ended or Differential |
| AS1528-BTDR | 功能描述:IC A/D 10-BIT 1-CH 150K 8-TDFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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