參數(shù)資料
型號: AS1527-BSOT
廠商: AUSTRIAMICROSYSTEMS AG
元件分類: ADC
英文描述: 10-bit ADC, 1-Channel, 73ksps; Package Type: SOIC-8
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: SOIC-8
文件頁數(shù): 13/21頁
文件大?。?/td> 751K
代理商: AS1527-BSOT
www.austriamicrosystems.com
Revision 1.03
13 - 21
AS1526/AS1527
Data Sheet
- Detailed Description
9. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CSN,
produce trailing zeros at DOUT and have no effect on the conversion process.
10. For minimum cycle time, clock out the data with 10.5 clock cycles at full speed using the rising edge of DOUT as
the EOC signal. Pull CSN high after reading the conversion’s LSB. After the specified minimum time (t
CS
) CSN can
be pulled low to initiate the next conversion.
Figure 25. Serial Interface Standard Cycle Timing Diagram
Figure 26. Serial Interface Minimum Cycle Timing Diagram
Figure 27. Detailed Serial Interface Timing Diagram
CSN
SCLK
DOUT
Conversion
In Progress
Hold
EOC
Track/Hold
Stage
Track
Clock Out Serial Data
Track
Cycle Time
Total = 13.7μs
Trailing
0s
Idle
0.24μs
t
CS
0μs
t
CONV
7.5μs
Hold
Interface
Idle
B9 B8 B7 B6 B5 B4 B3 B2 B1
B0 S1 S0
0μs
12.5 x 0.476μs = 5.95μs
Sub
Bits
Hold
Track/Hold
Stage
Track
Track
Hold
Total = 12.74μs
Cycle Time
DOUT
B9
B8
B7
B6
B5
B4
B3
B1
B0
CSN
EOC
Clock Out Serial Data
Idle
Interface
Idle
0.24μs
t
CS
7.5μs
t
CONV
0μs
10.5 x 0.476μs = 5μs
SCLK
B2
Conversion
In Progress
Track/Acquire
CSN
SCLK
DOUT
Internal
Track/Hold
t
CONV
t
AP
t
DV
t
STR
Hold
t
CSO
t
DO
t
CH
t
CL
t
CS
t
TR
Track/Acquire
B0
S1
S0
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