參數(shù)資料
型號(hào): AS1504-T
廠商: AUSTRIAMICROSYSTEMS AG
元件分類: DAC
英文描述: Octal, 8-bit, Mid-Scale Reset; Package Type: SOIC(150mil)-16
中文描述: 八進(jìn)制8位可編程低功耗DAC的具有關(guān)斷和中間刻度重置
封裝: SOIC(150mil)-16
文件頁(yè)數(shù): 10/17頁(yè)
文件大小: 471K
代理商: AS1504-T
www.austriamicrosystems.com
Revision 1.0
10 - 17
AS1504/AS1505
Data Sheet
- Detailed Description
Figure 15. Equivalent DAC Circuit
Programming The Output Voltage
The output voltage range is determined by the external reference connected to pins V
REFH
and V
REFL
(see
Figure 15
on page 10
for a simplified diagram of the equivalent DAC circuit).
V
REFL
for the AS1504 is internally connected to GND and therefore cannot be offset. Pin V
REFH
can be tied to V
DD
and
pin V
REFL
can be tied to GND establishing a basic rail-to-rail output voltage programming range. Other output ranges
are established by the use of different external voltage references.
The programmed output voltage is determined as:
V
OUT
(Dx) = (Dx)/256 x (V
REFH
– V
REFL
) + V
REFL
(EQ 2)
Where:
Dx is the data contained in the 8-bit DAC
x
latch.
For example, when V
REFH
= +5V and V
REFL
= 0V the output voltages will be generated per the codes listed in
Table 6
.
Table 6. Output Voltages
Data Bits
V
OUT
x
Output State (V
REFH
= +5V, V
REFL
= 0V)
255
4.98V
128
2.50V
1
0.02V
0
0.00V
Reference Inputs
The reference input pins (V
REFH
and V
REFL
) set the output voltage range of all eight DACs. For the AS1504, only pin
V
REFH
is available to establish a programmable full-scale output voltage.
Note:
The external reference voltage can be any value between 0 and V
DD
but must not exceed V
DD
.
The AS1505 uses pin V
REFL
to establish the zero-scale output voltage. Any voltage can be applied between 0 and
V
DD
. V
REFL
can be smaller or larger than V
REFH
since the DAC design uses fully bi-directional switches as shown in
Figure 15
. The input resistance to the DAC has a code dependent variation that has a nominal worst case measured at
55
h
, which is approximately 2k
Ω
. When V
REFH
is greater than V
REFL
, the REFL reference must be able to sink current
out of the DAC ladder, while the REFH reference is sourcing current into the DAC ladder. The DAC design minimizes
reference glitch current, thus maintaining minimum interference between DAC channels during code changes.
Full-Scale
Half-Scale (Mid-Scale Reset Value)
1 LSB
Zero-Scale
GND
V
REFL
DAC
Register
D7
D6
D0
V
REFH
LSB
MSB
P CH
N CH
2R
2R
2R
2R
R
R
To other DACs
Ox
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