參數(shù)資料
型號: APXS006A0X-SRDZ
廠商: LINEAGE POWER LLC
元件分類: 電源模塊
英文描述: 1-OUTPUT 33 W DC-DC REG PWR SUPPLY MODULE
封裝: ROHS COMPLIANT, SMT-10
文件頁數(shù): 7/25頁
文件大小: 746K
代理商: APXS006A0X-SRDZ
Data Sheet
November 22, 2010
12V Pico TLynxTM 6A: Non-isolated DC-DC Power Modules
4.5 – 14Vdc input; 0.59Vdc to 5.5Vdc output; 6A output current
LINEAGE POWER
15
Remote Sense feature is not being used, connect the
SENSE pin to the VOUT pin.
V
O(+)
TRIM
GND
R
trim
LOAD
V
IN(+)
ON/OFF
SENSE
Figure 45. Circuit configuration for programming
output voltage using an external resistor.
Voltage Margining
Output voltage margining can be implemented in the
12V Pico TLynx
TM 6A modules by connecting a
resistor, Rmargin-up, from the Trim pin to the ground pin
for margining-up the output voltage and by connecting
a resistor, Rmargin-down, from the Trim pin to output pin
for margining-down. Figure 46 shows the circuit
configuration for output voltage margining. The POL
Programming Tool, available at
www.lineagepower.com under the Design Tools
section, also calculates the values of Rmargin-up and
Rmargin-down for a specific output voltage and % margin.
Please consult your local Lineage Power technical
representative for additional details.
Vo
MODULE
GND
Trim
Q1
Rtrim
Rmargin-up
Q2
Rmargin-down
Figure 46. Circuit Configuration for margining
Output voltage.
Monotonic Start-up and Shutdown
The 12V Pico TLynx
TM 6A modules have monotonic
start-up and shutdown behavior for any combination of
rated input voltage, output current and operating
temperature range.
Startup into Pre-biased Output
The 12V Pico TLynx
TM 6A modules can start into a
prebiased output as long as the prebias voltage is 0.5V
less than the set output voltage. Note that prebias
operation is not supported when output voltage
sequencing is used.
Output Voltage Sequencing
The 12V Pico TLynx
TM 6A modules include a
sequencing feature, EZ-SEQUENCE that enables
users to implement various types of output voltage
sequencing in their applications. This is accomplished
via an additional sequencing pin. When not using the
sequencing feature, either tie the SEQ pin to VIN or
leave it unconnected.
When an analog voltage is applied to the SEQ pin, the
output voltage tracks this voltage until the output
reaches the set-point voltage. The final value of the
SEQ voltage must be set higher than the set-point
voltage of the module. The output voltage follows the
voltage on the SEQ pin on a one-to-one basis. By
connecting multiple modules together, multiple
modules can track their output voltages to the voltage
applied on the SEQ pin.
For proper voltage sequencing, first, input voltage is
applied to the module. The On/Off pin of the module is
left unconnected (or tied to GND for negative logic
modules or tied to VIN for positive logic modules) so
that the module is ON by default. After applying input
voltage to the module, a minimum 10msec delay is
required before applying voltage on the SEQ pin. This
delay gives the module enough time to complete its
internal power-up soft-start cycle. During the delay
time, the SEQ pin should be held close to ground
(nominally 50mV ± 20 mV). This is required to keep the
internal op-amp out of saturation thus preventing
output overshoot during the start of the sequencing
ramp. By selecting resistor R1 (see fig. 47) according
to the following equation
05
.
0
24950
1
=
IN
V
R
ohms,
the voltage at the sequencing pin will be 50mV when
the sequencing signal is at zero.
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