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參數(shù)資料
| 型號(hào)： | APM4550KC-TRL |
| 廠商： | Anpec Electronics Corporation |
| 英文描述： | Dual Enhancement Mode MOSFET (N- and P-Channel) |
| 中文描述： | 雙增強(qiáng)型MOS管（N溝道和P溝道） |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 245K |
| 代理商： | APM4550KC-TRL |
Copyright
ANPEC Electronics Corp.
Rev. A.1 - May, 2007
www.anpec.com.tw
3
APM4550K
Notes:
a : Pulse test ; pulse width
≤
300
μ
s, duty cycle
≤
2
%.
b : Guaranteed by design, not subject to production testing.
Electrical Characteristics ( Cont.)
(T
A
= 25
°
C unless otherwise noted)
APM4550K
Symbol
Parameter
Test Condition
Min.
Typ. Max.
Unit
Diode Characteristics
I
SD
=2.5A, V
GS
=0V
I
SD
=-2A, V
GS
=0V
N-Ch
0.8
1.3
V
SD
a
Diode Forward Voltage
P-Ch
-0.8
-1.3
V
N-Ch
8
t
rr
Reverse Recovery Time
P-Ch
13
ns
N-Ch
3
Q
rr
Reverse Recovery
Charge
N-Channel
I
SD
=7A, dl
SD
/dt=100A/
μ
s
N-Channel
I
SD
=-5A, dl
SD
/dt=100A/
μ
s
P-Ch
5
nC
Dynamic Characteristics
b
N-Ch
2
R
G
Gate Resistance
V
GS
=0V,V
DS
=0V,F=1MHz
P-Ch
8.3
N-Ch
620
C
iss
Input Capacitance
P-Ch
590
N-Ch
85
C
oss
Output Capacitance
P-Ch
95
N-Ch
65
C
rss
Reverse Transfer
Capacitance
N-Channel
V
GS
=0V,
V
DS
=15V,
Frequency=1.0MHz
P-Channel
V
GS
=0V,
V
DS
=-15V,
Frequency=1.0MHz
P-Ch
70
pF
N-Ch
6
11
t
d(ON)
Turn-on Delay Time
P-Ch
5
9
N-Ch
10
18
T
r
Turn-on Rise Time
P-Ch
12
23
N-Ch
22
41
t
d(OFF)
Turn-off Delay Time
P-Ch
27
50
N-Ch
3
6
T
f
Turn-off Fall Time
N-Channel
V
DD
=15V, R
L
=15
,
I
DS
=1A, V
GEN
=10V,
R
G
=6
P-Channel
V
DD
=-15V, R
L
=15
,
I
DS
=-1A, V
GEN
=-10V,
R
G
=6
P-Ch
13
24
ns
Gate Charge Characteristics
b
N-Ch
14
19
Q
g
Total Gate Charge
P-Ch
11
15
N-Ch
1.4
Q
gs
Gate-Source Charge
P-Ch
1.3
N-Ch
2.6
Q
gd
Gate-Drain Charge
N-Channel
V
DS
=15V, V
GS
=10V,
I
DS
=7A
P-Channel
V
DS
=-15V, V
GS
=-10V,
I
DS
=-5A
P-Ch
2.7
nC
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