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參數(shù)資料
| 型號： | APCI-SER4 |
| 英文描述： | PCI-BUS I/O CARD |
| 中文描述： | PCI總線的I / O卡 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 251K |
| 代理商： | APCI-SER4 |
2192-09125-000-000
Page 6
J605 APCI-ADADIO
LK1: Psedo Differential Ground Connection
LK3: Differential/Single-Ended Input selection
LK5-6: DAC Output range
LK5 and LK6 are used to select the output range for DAC1 and DAC0 respectively. The range settings
are as below:
LK7-8 and LK18 ADC Input Ranges
These links are used to select the ADC input range. The range settings are as below:
Note:
- Both links should not be fitted in position B on LK7 and LK8.
LK9-11 ADC Trigger Sources
These links are used to select between the three different ADC trigger sources. Each trigger source
is enabled when the link is fitted. To ensure correct operation only one link should be fitted.
LK12-15 Digital I/O Reset State
These links select the state of the digital I/O lines at reset in nibble (4 bit) groups.
The link associated with each nibble is shown below:
LK15
LK14
LK13
LK12
Digital I/O lines 0-3
Digital I/O lines 4-7
Digital I/O lines 8-11
Digital I/O lines 12-15
Note:
If a nibble is to be used as an Input the corresponding link should be placed in position B to
ensure damage is not caused to the card or external circuitry.
LK16 Counter/Timer Channel 0 clock source
This link selects the clock source for counter timer channel 0.
Fit
Omit
APCI-ADADIOCS, fit only if inputs are isolated from 0VA
APCI-ADADIOCD, Differential inputs
A
B
Differential - APCI-ADADIOCD
Single Ended - APCI-ADADIOCS
+LK9
LK10
LK11
Enable Software trigger
Enable Hardware trigger
Enable Counter/timer channel 0 trigger
+A
B
None
-5V to +5V
0V to +5V
0V to +10V
A
+B
Sets output low
Sets output high
LK16A
+LK16B
Clocked by output from Counter/timer channel 2
1MHZ Clock
LK7
+A
A
B
A
LK8
+A
B
A
B
LK18
+Omit
Omit
Omit
Fit
Range
-5V to +5V
0V to +10V
-10V to +10V
0V to +5V
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