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參數(shù)資料
| 型號(hào)： | APCI-ADADIOCS |
| 英文描述： | PCI-BUS I/O CARD |
| 中文描述： | PCI總線的I / O卡 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 251K |
| 代理商： | APCI-ADADIOCS |
Interrupts
The APCI-ADADIO has one interrupt output signal which is routed to an IRQ line during the PCI BIOS
initialisation. This interrupt line is expanded on board to provide two interrupt sources. One of these
interrupts is connected to the ADC conversion complete signal and the other is connected to the
output of counter/timer channel 1.
If a counter/timer interrupt is generated a write sequence to Index register 8 must be executed in
order to clear the pending interrupt. The ADC Interrupt is cleared when the high byte data is
accessed.
A PCI BIOS call can be used to determine the IRQ signal assigned to this board.
Analogue to Digital Convertor
The APCI-ADADIO contains a single 12-bit successive approximation analogue to digital convertor.
The input to this device is connected to a 8 way (APCI-ADADIOCD) or 16 way Multiplexer (APCI-
ADADIOCS). Prior to an AD conversion the appropriate channel can be selected by writing to the
Multiplexer Channel Select register (Index 1).
The ADC may be triggered from three different sources, selected by links LK9-11. Only one of these
links should be fitted at any time to ensure correct operation. The three sources are:-
1. Software trigger, initiated by an I/O write sequence.
2. Hardware trigger from an external TTL input (/RCONV), approximately 1-2 uS low pulse.
3. Periodic timer, programmed from the on-board counter/timer channel 0.
The following sequence can be used to perform an A/D conversion when using the software trigger
mode.
1. Write 01H to the BASE address.
2. Write to BASE+1 with the Multiplexer value for the appropriate channel.
3. Wait for approximately 50uSec for the input to settle.
4. Write 00H to the BASE address.
5. Write to BASE+1 (any value) to start conversion.
6. Wait for approximately 20uSec for the conversion to complete.
7. Read BASE+1 and check bit 0 is at logic 0 i.e. conversion completed.
8. Read BASE+2 ADC data low nibble (bits 0-3).
9. Read BASE+3 ADC data high byte (bits 4-11).
The hardware trigger mode uses /RCONV on PL1 and the periodic timer mode uses counter/timer
channel 0 output to trigger the ADC. Conversion is initiated from these sources when /RCONV or
OUT0 are low. To ensure that the ADC does not perform multiple conversions the hardware and timer
pulses must be greater than 250nS and less than 6uS.
Maximum data throughput can be obtained by triggering a new conversion before data has been
read from the last conversion. To ensure that the ADC data registers contain the data from the last
conversion they must be read within 6uS of triggering a new conversion.
Digital to Analogue Convertor
The APCI-ADADIO contains two 12-bit digital to analogue convertors. On-board links can be used to
select between three possible output ranges +/- 5V, 0-5V and 0-10V. The DAC values are updated by
Page 4
2192-09125-000-000
J605 APCI-ADADIO
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