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參數(shù)資料
| 型號(hào)： | APCI-ADADIOCS |
| 英文描述： | PCI-BUS I/O CARD |
| 中文描述： | PCI總線的I / O卡 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 251K |
| 代理商： | APCI-ADADIOCS |
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Page 2
Operation
PCI Bus Interface
The PCI bus is a high speed alternative to ISA bus, it has been designed to overcome some of the
limitations of ISA bus, and provide faster throughput for I/O intensive peripheral devices. PCI bus
also supports Plug and Play configuration which allows the system software to allocate resources
during initialisation helping to overcome address conflicts, which might exist in a system.
The APCI-ADADIO uses a single chip PCI bus slave controller which is designed and manufactured by
PLX Technology. This device has been designed to fully support the PCI 2.1 specification and
provides plug and play software capabilities. During power-up initialisation the PCI BIOS will detect
the card and assign a unique I/O address location and interrupt line. This ensures that there are no
resource conflicts on the PCI bus. Multiple cards are supported through this mechanism without the
need for address decode links.
The PLX device contains a standard type 00H configuration space header. The table below shows the
registers within this header which are required for configuration of the APCI-ADADIO.
Configuration Space Header
These registers can be accessed using PCI BIOS function calls.
I/O Map
The APCI-ADADIO uses an indexed addressing scheme to access the on-board devices and special
function registers. Two consecutive I/O locations are required to implement this scheme, the BASE
address is used to set the index value and the BASE+1 address is used to access the device. ADC and
DAC data is accessed via a dedicated pair of registers which are not part of the indexing scheme.
The I/O base address is set by the PCI BIOS during initialisation (refer to the PCI Bus section of this
manual for details). A PCI BIOS function call may be used to determine the base address once the
system has been initialised. Multiple boards may be used in a system as each will be given a unique
I/O base address.
2192-09125-000-000
J605 APCI-ADADIO
Offset
00-01H
02-03H
18-1BH
2C-2DH
2E-2FH
3CH
Register
Name
Vendor ID
Device ID
Base Address Register
Subsystem Vendor ID
Subsystem ID
Interrupt Line
Description
ID of PCI device manufacturer
ID of PCI device
I/O base address assigned to card
ID of board manufacturer
ID of Board
Interrupt line assigned to device
Value
10B5H (PLX Technology)
9050H
0000xxxx
13ABH (ARCOM)
0605H (APCI-ADADIO)
0x
I/O Address
Base
Base+1
Base+2
Base+3
Function
Index register
Control/Status
ADC/DAC LSB Data
ADC/DAC MSB Data
Read/Write
Write
Read/Write
Read/Write
Read/Write
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PDF描述 |
|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| APCI-IB40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI-BUS I/O CARD |
| APCI-RELAY8/IN8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI-BUS I/O CARD |
| APCI-SER4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI-BUS I/O CARD |
| APCITE | 制造商:Pentair Technical Products / Hoffman 功能描述:Operator Adapter, I.T.E. , for I-T-E Max-Flex, Steel |
| APCMB012 | 制造商:Amphenol Corporation 功能描述:MS3106E24-AJP W/OUT CNTS |
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