ProASICPLUS Flash Family FPGAs 4- 2 v5.9 v5.1 MIL-STD-883 was added to the datas" />
參數資料
型號: APA750-FGG896I
廠商: Microsemi SoC
文件頁數: 80/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 750K 896-FBGA
標準包裝: 27
系列: ProASICPLUS
RAM 位總計: 147456
輸入/輸出數: 562
門數: 750000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 896-BGA
供應商設備封裝: 896-FBGA(31x31)
ProASICPLUS Flash Family FPGAs
4- 2
v5.9
v5.1
MIL-STD-883 was added to the datasheet.
N/A
VCC and VCCI were changed to VDDP.
N/A
v5.0
In the "208-Pin PQFP" table, the following pin numbers have been updated:
Pin Number
Function
24
I/O / GL2
30
I/O / GL1
In the "208-Pin CQFP" table, the following pin numbers have been updated:
Pin Number
Function
23
I/O / GLMX1
24
I/O / GL2
28
PPECL1 / Input
30
I/O / GL1
128
I/O / GL3
129
PPECL2 / Input
134
I/O / GL4
135
I/O / GLMX2
v4.1
In the "624-Pin CCGA/LGA" table, the following pin numbers have been updated:
Pin Number
Function
M6
I/O / GL2
M7
I/O / GLMX1
M19
I/O / GLMX2
M20
I/O / GL4
N5
PPECL1 / Input
N6
I/O / GL1
N20
I/O / GL3
N21
PPECL2 / Input
MIL-STD 883B data will be added into this datasheet after the MIL-STD 883B qualification is
complete.
Green packaging information in the "Ordering Information" section was updated.
The "Temperature Grade Offerings" table was updated for the CG624.
The 3.3 V column in Table 2-3 was updated.
The note was removed from Table 2-4 I/O Features.
The first bullet in the "ProASICPLUS Clock Management System" section was updated.
The first paragraph in the "Performance Retention" section was updated.
Mixed Voltage was removed from Table 2-20 Recommended Maximum Operating
Mixed Mode Voltage was removed from Table 2-22 and the Military/MIL-STD-883B column was
updated.
Previous version
Changes in current version (v5.9)
Page
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