ProASICPLUS Flash Family FPGAs v5.9 2-49 Table 2-41 Worst-Case Military " />
參數(shù)資料
型號: APA600-PQ208
廠商: Microsemi SoC
文件頁數(shù): 134/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 600K 208-PQFP
標準包裝: 24
系列: ProASICPLUS
RAM 位總計: 129024
輸入/輸出數(shù): 158
門數(shù): 600000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
ProASICPLUS Flash Family FPGAs
v5.9
2-49
Table 2-41 Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
Macro Type
Description
Max. tINYH
1
Max. tINYL
2
Std.
GL33
3.3V, CMOS Input Levels3, No Pull-up Resistor
1.1
GL33S
3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger
1.1
PECL
PPECL Input Levels
1.1
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP =2.3 V for delays.
Table 2-42 Worst-Case Military Conditions
VDDP = 2.3V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
Macro Type
Description
Max. tINYH
1
Max. tINYL
2
Std.
GL25LP
2.5V, CMOS Input Levels3, Low Power
1.0
1.1
GL25LPS
2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger
1.4
1.0
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP = 2.3 V for delays.
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