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參數(shù)資料
| 型號(hào)： | APA600-PQ208 |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 124/178頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA PROASIC+ 600K 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | ProASICPLUS |
| RAM 位總計(jì)： | 129024 |
| 輸入/輸出數(shù)： | 158 |
| 門數(shù)： | 600000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
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ProASICPLUS Flash Family FPGAs
v5.9
1-1
Device Family Overview
The ProASICPLUS family of devices, Actel’s second-
generation family of flash FPGAs, offers enhanced
performance over Actel’s ProASIC family. It combines the
advantages of ASICs with the benefits of programmable
devices through nonvolatile flash technology. This
enables engineers to create high-density systems using
existing ASIC or FPGA design flows and tools. In addition,
the ProASICPLUS family offers a unique clock conditioning
circuit based on two on-board phase-locked loops (PLLs).
The family offers up to one million system gates,
supported with up to 198 kbits of two-port SRAM and up
to 712 user I/Os, all providing 50 MHz PCI performance.
Advantages
to
the
designer
extend
beyond
performance. Unlike SRAM-based FPGAs, four levels of
routing hierarchy simplify routing, while the use of flash
technology allows all functionality to be live at power-
up. No external boot PROM is required to support device
programming. While on-board security mechanisms
prevent
access
to
the
program
information,
reprogramming can be performed in-system to support
future design iterations and field upgrades. The device’s
architecture mitigates the complexity of ASIC migration
at higher user volume. This makes ProASICPLUS a cost-
effective solution for applications in the networking,
communications, computing, and avionics markets.
The ProASICPLUS family achieves its nonvolatility and
reprogrammability through an advanced flash-based
0.22
μm LVCMOS process with four layers of metal.
Standard
CMOS
design
techniques
are
used
to
implement logic and control functions, including the
PLLs and LVPECL inputs. This results in predictable
performance compatible with gate arrays.
The
ProASICPLUS
architecture
provides
granularity
comparable to gate arrays. The device core consists of a
Sea-of-Tiles
. Each tile can be configured as a flip-flop,
latch, or three-input/one-output logic function by
programming the appropriate Flash switches. The
combination
of
fine
granularity,
flexible
routing
resources, and abundant flash switches allows 100%
utilization and over 95% routability for highly congested
designs. Tiles and larger functions are interconnected
through a four-level routing hierarchy.
Embedded two-port SRAM blocks with built-in FIFO/RAM
control logic can have user-defined depths and widths.
Users can also select programming for synchronous or
asynchronous operation, as well as parity generations or
checking.
The unique clock conditioning circuitry in each device
includes two clock conditioning blocks. Each block
provides a PLL core, delay lines, phase shifts (0
° and
180
°), and clock multipliers/dividers, as well as the
circuitry needed to provide bidirectional access to the
PLL.
The
PLL
block
contains
four
programmable
frequency dividers which allow the incoming clock signal
to be divided by a wide range of factors from 1 to 64.
The clock conditioning circuit also delays or advances the
incoming reference clock up to 8 ns (in increments of
0.25 ns). The PLL can be configured internally or
externally during operation without redesigning or
reprogramming the part. In addition to the PLL, there
are two LVPECL differential input pairs to accommodate
high-speed clock and data inputs.
To support customer needs for more comprehensive,
lower-cost,
board-level
testing,
Actel’s
ProASICPLUS
devices are fully compatible with IEEE Standard 1149.1
for test access port and boundary-scan test architecture.
For more information concerning the flash FPGA
implementation, please refer to the "Boundary Scan
ProASICPLUS devices are available in a variety of high-
performance plastic packages. Those packages and the
performance features discussed above are described in
more detail in the following sections.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT25128B-XHL-B | IC EEPROM 128KBIT 20MHZ 8TSSOP |
| APA600-PQG208 | IC FPGA PROASIC+ 600K 208-PQFP |
| M1AFS1500-1FG676 | IC FPGA 8MB FLASH 1.5M 676-FBGA |
| AT25128B-SSHL-B | IC EEPROM 128KBIT 20MHZ 8SOIC |
| AFS1500-1FG676 | IC FPGA 8MB FLASH 1.5M 676-FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| APA600-PQ208A | 功能描述:IC FPGA PROASIC+ 600K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| APA600-PQ208I | 功能描述:IC FPGA PROASIC+ 600K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| APA600-PQ208M | 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 600K GATES 180MHZ 0.22UM 2.5V 208PQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA PROASICPLUS 600K GATES 180MHZ 0.22UM 2.5V 208PQFP - Trays |
| APA600-PQ896A | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Automotive-Grade ProASIC Flash Family FPGAs |
| APA600-PQB | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
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