ProASICPLUS Flash Family FPGAs
2- 42
v5.9
Tristate Buffer Delays
Figure 2-23 Tristate Buffer Delays
Table 2-27 Worst-Case Commercial Conditions
VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70°C
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Max.
tENZH
3
Max.
tENZL
4
Units
Std.
OTB33PH
3.3 V, PCI Output Current, High Slew Rate
2.0
2.2
2.0
ns
OTB33PN
3.3 V, High Output Current, Nominal Slew Rate
2.2
2.9
2.4
2.1
ns
OTB33PL
3.3 V, High Output Current, Low Slew Rate
2.5
3.2
2.7
2.8
ns
OTB33LH
3.3 V, Low Output Current, High Slew Rate
2.6
4.0
2.8
3.0
ns
OTB33LN
3.3 V, Low Output Current, Nominal Slew Rate
2.9
4.3
3.2
4.1
ns
OTB33LL
3.3 V, Low Output Current, Low Slew Rate
3.0
5.6
3.3
5.5
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. tENZH = Enable-to-Pad, Z to High
4. tENZL = Enable-to-Pad, Z to Low
Table 2-28 Worst-Case Commercial Conditions
VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70°C
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Max.
tENZH
3
Max.
tENZL
4
Units
Std.
OTB25LPHH
2.5 V, Low Power, High Output Current, High Slew Rate5
2.0
2.1
2.3
2.0
ns
OTB25LPHN
2.5 V, Low Power, High Output Current, Nominal Slew Rate5
2.4
3.0
2.7
2.1
ns
OTB25LPHL
2.5 V, Low Power, High Output Current, Low Slew Rate5
2.9
3.2
3.1
2.7
ns
OTB25LPLH
2.5 V, Low Power, Low Output Current, High Slew Rate5
2.7
4.6
3.0
2.6
ns
OTB25LPLN
2.5 V, Low Power, Low Output Current, Nominal Slew Rate5
3.5
4.2
3.8
ns
OTB25LPLL
2.5 V, Low Power, Low Output Current, Low Slew Rate5
4.0
5.3
4.2
5.1
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. tENZH = Enable-to-Pad, Z to High
4. tENZL = Enable-to-Pad, Z to Low
5. Low power I/O work with VDDP = 2.5 V ±10% only. VDDP = 2.3 V for delays.
PAD
A
OTBx
A
50%
PAD
VOL
VOH
50%
t
DLH
50%
t
DHL
EN
50%
PAD
VOL
50%
t
ENZL
50%
10%
EN
50%
PAD
GND
V
OH
50%
t
ENZH
50%
90%
VDDP
35 pF
EN