ProASICPLUS Flash Family FPGAs v5.9 2-73 Pin Description User Pins I/O User Inpu" />
參數(shù)資料
型號： APA075-TQ144I
廠商： Microsemi SoC
文件頁數(shù)： 161/178頁
文件大小： 0K
描述： IC FPGA PROASIC+ 75K 144-TQFP
標準包裝： 60
系列： ProASICPLUS
RAM 位總計： 27648
輸入/輸出數(shù)： 107
門數(shù)： 75000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
ProASICPLUS Flash Family FPGAs
v5.9
2-73
Pin Description
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible
with
standard
LVTTL
and
LVCMOS
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
NC
No Connect
To maintain compatibility with other Actel ProASICPLUS
products, it is recommended that this pin not be
connected to the circuitry on the board.
GL
Global Pin
Low skew input pin for clock or other global signals. This
pin can be configured with an internal pull-up resistor.
When it is not connected to the global network or the
clock conditioning circuit, it can be configured and used
as a normal I/O.
GLMX
Global Multiplexing Pin
Low skew input pin for clock or other global signals. This
pin can be used in one of two special ways (refer to
When the external feedback option is selected for the
PLL block, this pin is routed as the external feedback
source to the clock conditioning circuit.
In applications where two different signals access the
same global net at different times through the use of
GLMXx and GLMXLx macros, this pin will be fixed as one
of the source pins.
This pin can be configured with an internal pull-up
resistor. When it is not connected to the global network
or the clock conditioning circuit, it can be configured and
used as any normal I/O. If not used, the GLMXx pin will
be configured as an input with pull-up.
Dedicated Pins
GND
Ground
Common ground supply voltage.
VDD
Logic Array Power Supply Pin
2.5 V supply voltage.
VDDP
I/O Pad Power Supply Pin
2.5 V or 3.3 V supply voltage.
TMS
Test Mode Select
The TMS pin controls the use of boundary-scan circuitry.
This pin has an internal pull-up resistor.
TCK
Test Clock
Clock input pin for boundary scan (maximum 10 MHz). Actel
recommends adding a nominal 20 k
Ω pull-up resistor to this
pin.
TDI
Test Data In
Serial input for boundary scan. A dedicated pull-up
resistor is included to pull this pin high when not being
driven.
TDO
Test Data Out
Serial output for boundary scan. Actel recommends
adding a nominal 20k
Ω pull-up resistor to this pin.
TRST
Test Reset Input
Asynchronous,
active
low
input pin
for
resetting
boundary-scan circuitry. This pin has an internal pull-up
resistor. For more information, please refer to Power-up
Behavior of ProASICPLUS Devices application note.
Special Function Pins
RCK
Running Clock
A free running clock is needed during programming if
the programmer cannot guarantee that TCK will be
uninterrupted. If not used, this pin has an internal pull-
up and can be left floating.
NPECL
User Negative Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
PPECL
User Positive Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
AVDD
PLL Power Supply
Analog VDD should be VDD (core voltage) 2.5 V (nominal)
and be decoupled from GND with suitable decoupling
capacitors to reduce noise. For more information, refer
application note. If the clock conditioning circuitry is not
used in a design, AVDD can either be left floating or tied
to 2.5 V.
AGND
PLL Power Ground
The analog ground can be connected to the system
ground. For more information, refer to Actel’s Using
ProASICPLUS Clock Conditioning Circuits application note.
If the PLLs or clock conditioning circuitry are not used in
a design, AGND should be tied to GND.
相關PDF資料
PDF描述
ABC43DRYH-S93 CONN EDGECARD 86POS DIP .100 SLD
A42MX09-PLG84A IC FPGA MX SGL CHIP 14K 84-PLCC
ESC65DRTS-S734 CONN EDGECARD 130PS DIP .100 SLD
EMC49DRAS CONN EDGECARD 98POS R/A .100 SLD
A42MX09-PQG160 IC FPGA MX SGL CHIP 14K 160-PQFP
相關代理商/技術參數(shù)
參數(shù)描述
APA075-TQ896A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Automotive-Grade ProASIC Flash Family FPGAs
APA075-TQB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA075-TQES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA075-TQG100 功能描述:IC FPGA PROASIC+ 75K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
APA075-TQG100A 功能描述:IC FPGA PROASIC+ 75K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17）
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*