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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | APA075-FGG144I |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 100/178闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA PROASIC+ 75K 144-FBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 160 |
| 绯诲垪锛� | ProASICPLUS |
| RAM 浣嶇附瑷�(j矛)锛� | 27648 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 100 |
| 闁€鏁�(sh霉)锛� | 75000 |
| 闆绘簮闆诲锛� | 2.3 V ~ 2.7 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 144-LBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 144-FPBGA锛�13x13锛� |
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ProASICPLUS Flash Family FPGAs
2- 18
v5.9
PLL Electrical Specifications
Parameter
Value TJ 鈮� 鈥�40掳C
Value TJ > 鈥�40掳C
Notes
Frequency Ranges
Reference Frequency fIN (min.)
2.0 MHz
1.5 MHz
Clock conditioning circuitry (min.) lowest input
frequency
Reference Frequency fIN (max.)
180 MHz
Clock conditioning circuitry (max.) highest input
frequency
OSC Frequency fVCO (min.)
60
24 MHz
Lowest output frequency voltage controlled
oscillator
OSC Frequency fVCO (max.)
180
180 MHz
Highest output frequency voltage controlled
oscillator
Clock Conditioning Circuitry fOUT (min.)
fIN 鈮� 40 = 18 MHz
fIN > 40 = 16 MHz
6 MHz
Lowest output frequency clock conditioning
circuitry
Clock Conditioning Circuitry fOUT (max.) 180
180 MHz
Highest output frequency clock conditioning
circuitry
Acquisition Time from Cold Start
Acquisition Time (max.)
80
渭s
30
渭sf
VCO 鈮� 40 MHz
Acquisition Time (max.)
80
渭s
80
渭sf
VCO > 40 MHz
Long Term Jitter Peak-to-Peak Max.*
Temperature
Frequency MHz
fVCO<
10
10<fV
CO<60
fVCO
>60
25掳C (or higher)
卤1%
卤2%
卤1% Jitter(ps) = Jitter(%)*period
For example:
Jitter in picoseconds at 100 MHz
= 0.01 * (1/100E6) = 100 ps
0掳C
卤1.5% 卤2.5% 卤1%
鈥�40掳C
卤2.5% 卤3.5% 卤1%
鈥�55掳C
卤2.5% 卤3.5% 卤1%
Power Consumption
Analog Supply Power (max.*)
6.9 mW per PLL
Digital Supply Current (max.)
7
渭W/MHz
Duty Cycle
50% 卤0.5%
Input Jitter Tolerance
5% input period (max.
5 ns)
Maximum jitter allowable on an input
clock to acquire and maintain lock.
Note: *High clock frequencies (>60 MHz) under typical setup conditions
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| APA075-FG144I | IC FPGA PROASIC+ 75K 144-FBGA |
| M1AGL600V5-FGG256 | IC FPGA 1KB FLASH 600K 256-FBGA |
| AGL600V5-FG256 | IC FPGA 1KB FLASH 600K 256-FBGA |
| M1AGL600V5-FG256 | IC FPGA 1KB FLASH 600K 256-FBGA |
| AGL600V5-FGG256 | IC FPGA 1KB FLASH 600K 256-FBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| APA075-FGGB | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |
| APA075-FGGES | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |
| APA075-FGGI | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |
| APA075-FGGM | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |
| APA075-FGGPP | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |
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