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參數資料
| 型號： | AP-752 |
| 英文描述： | AP-752 - AP-752 The Advantages of Using the 82371SB PCI ISA IDE Xcelerator (PIIX3) with the Intel 430HX PCIset in Embedded Designs |
| 中文描述： | 美聯社- 752 -美聯社- 752采用了Intel 430HX在嵌入式設計PCIset的ISA的82371SB的PCI IDE的Xcelerator（PIIX3）的優(yōu)勢 |
| 文件頁數： | 6/7頁 |
| 文件大?。?/td> | 39K |
| 代理商： | AP-752 |
AP-752
2
The PIIX3 provides positive decode (chip selects) and X-
Bus buffer control for a real time clock, a keyboard
controller, and BIOS for PCI ISA initiated cycles. In
addition, the PIIX3 integrates the system reset logic for
the system. It generates CPURST, PCIRST#, and
RSTDRV during power up (PWROK) and whenever a
hard reset is initiated through the RC register. It also
generates the NMI and SMI# signals to the processor.
All of these features of the PIIX3 are integrated in a single
208-lead QFP package. This is very important in
embedded designs where board space is at a premium.
Intel, at this time, does not sell the PIIX3 separate from
the TXC. Therefore, the PIIX3, and related technical
support, will be available as long as the 430HX PCIset is
available.
4.0
Designing without the PIIX3
If the PIIX3 is not implemented with the 430HX PCIset,
several features that are typically supported by the PIIX3
and that are required in certain embedded designs must be
provided by other means. This section discusses some
design considerations with two alternatives: using the
Super I/O* Controller and using another PCI-to-ISA
bridge.
4.1
Using a Super I/O Controller
Using a Super I/O Controller is not new to the design
world, but using the Super I/O Controller in a design that
does not have an ISA bus interface is new. Using a Super
I/O Controller in this type of design raises many issues:
The Super I/O Controller must be interfaced with the
PCI bus. This type of Super I/O Controller is not
common in the market. A standard ISA Super I/O
Controller can be used but requires additional logic to
interface to the PCI bus.
Most of the Super I/O Controllers do not have the
interrupt, DMA, and IDE controllers and/or a timer
counter. Separate devices may have to be added to the
design.
A PCI-to-Flash controller must be provided to access
boot ROM code.
A special software interface must be implemented for
utilizing the processor’s power management capabil-
ities and handling the processor interface signals,
such as different types of resets, NMI, and SMI#
signals.
These considerations complicate and add more cost to the
design, including the components cost and the non-
recurring-engineering (NRE) cost. They also increase the
board space. Additional devices on the PCI bus may cause
electrical loading problems. In addition, the availability of
these components may not be guaranteed for long-term
embedded support.
4.2
Using Another PCI-to-ISA Bridge
A second workaround method is to use a PCI-to-ISA
bridge other than the PIIX3. Considerations in imple-
menting this type of design include:
The PCI-to-ISA bridge timing specifications must be
compatible with those of the PIIX3 to enable
interfacing with the TXC.
The availability of the new bridge may not be
guaranteed for long-term embedded support.
Intel cannot be responsible for the technical support
of these types of designs.
5.0
Conclusion
Using the PIIX3 in embedded designs that use the 430HX
PCIset makes the embedded design much easier to
implement. Designing with the PIIX3 reduces the cost and
embedded total number of components in the design. The
PIIX3 will be available in the embedded market as long as
the 430HX PCIset is available. Intel recommends and
supports using the complete 430HX PCIset.
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