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| 型號： | AP-752 |
| 英文描述： | AP-752 - AP-752 The Advantages of Using the 82371SB PCI ISA IDE Xcelerator (PIIX3) with the Intel 430HX PCIset in Embedded Designs |
| 中文描述： | 美聯(lián)社- 752 -美聯(lián)社- 752采用了Intel 430HX在嵌入式設(shè)計PCIset的ISA的82371SB的PCI IDE的Xcelerator（PIIX3）的優(yōu)勢 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 39K |
| 代理商： | AP-752 |
AP-752
1
1.0
Introduction
This application note explains the advantages of using the
82371SB PCI ISA IDE Xcelerator (PIIX3) in embedded
designs that use the Intel 430HX PCIset. It highlights
some of the important functions and features of the PIIX3
and addresses some of the design considerations when
eliminating the PIIX3 from an embedded design.
2.0
Intel 430HX PCIset Overview
The Intel 430HX PCIset consists of the 82439HX System
Controller (TXC) and the 82371SB PCI ISA IDE
Xcelerator (PIIX3). The TXC is a single-chip host-to-PCI
bridge and provides the second-level cache control and
DRAM control functions. The second-level (L2) cache
controller supports a write-back cache policy for cache
sizes of 256 Kbytes and 512 Kbytes. The cache controller
also supports cacheless designs. The cache memory is
implemented with synchronous pipelined burst SRAMs.
An external Tag RAM is used for the address tag and an
internal Tag RAM is used for the cache line status bits.
The TXC provides a 64/72-bit data path to main memory
and memory sizes up to 512 Mbytes. The DRAM
controller provides eight rows and optional DRAM error
detection/correction or parity.
The TXC’s optimized PCI interface allows the processor
to sustain the highest possible bandwidth to the graphics
frame buffer at all frequencies. Using the snoop ahead
feature, the TXC allows PCI masters to achieve full PCI
bandwidth. For increased system performance, the TXC
contains read prefetch and posted write buffers.
The PIIX3 is a multi-function PCI device that implements
a PCI-to-ISA bridge function and a PCI IDE function. The
PIIX3 also implements a Universal Serial Bus host/hub
function.
3.0
PIIX3 Features
As a PCI-to-ISA bridge, the PIIX3 integrates many
common I/O functions found in ISA-based PC systems.
These include a seven-channel DMA controller, two
82C59 interrupt controllers, an 8254 timer counter, and
power management support.
In addition to compatible transfers, each DMA channel
supports type F transfers. Edge/Level interrupts and
interrupt steering are supported for PCI plug-and-play
compatibility. The PIIX3 can be programmed to allow the
PCI active low interrupts (PIRQ[D:A]#) to be internally
routed to one of 11 interrupts (IRQ[15,14,12:9,7:3]). In
addition, the motherboard interrupt (MIRQ0) can be
routed to any of the 11 interrupts.
The PIIX3 supports two IDE connectors for up to four
IDE devices, providing an interface for IDE hard disks
and CD ROMs.
The PIIX3 contains a Universal Serial Bus (USB) host
controller that is UHCI compatible. The host controller’s
root hub has two programmable UBS ports. The PIIX3
can support a stand-alone I/O APIC device on the ISA X-
Bus. It provides the chip select signal (APICCS#) for the
I/O APIC and the handshake signals to maintain buffer
coherency in the I/O APIC environment.
The PIIX3 contains three counters that are equivalent to
those found in the 82C54 programmable interval timer.
The three counters are contained in one PIIX3 timer unit,
referred to as
Timer-1
. Each counter output provides a key
system timer interrupt for a time-of-day, diskette time-
out, or other system timing function. Counter 1 generates
a refresh request signal and Counter 2 generates the tone
for the speaker.
The PIIX3 has extensive power management capability,
permitting a system to operate in a low power state
without being powered down. The PIIX3 can put the
processor in a low power state by asserting the STPCLK#
signal, which is an interrupt to the processor. Once the
STPCLK# interrupt is executed, the processor enters the
stop grant state. In this state, the processor’s internal
clocks are disabled and instruction execution is stopped.
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