參數(shù)資料
型號(hào): AOZ1013
廠商: ALPHA
英文描述: EZBuck TM 3A Simple Buck Regulator
中文描述: EZBuck商標(biāo)3A條簡(jiǎn)單的降壓穩(wěn)壓器
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 578K
代理商: AOZ1013
^lwNMNP
February 2006
www.aosmd.com
Page 11 of 16
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly
decided by capacitor ESR and inductor ripple current.
The output ripple voltage calculation can be further
simplified to:
I
V
=
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric
type of ceramic, or other low ESR tantalum are
recommended to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It
can be calculated by:
CO
L
O
ESR
×
12
_
L
RMS
CO
I
I
=
Usually, the ripple current rating of the output
capacitor is a smaller issue because of the low
current stress. When the buck inductor is selected to
be very small and inductor ripple current is high,
output capacitor could be overstressed.
Loop Compensation
The AOZ1013 employs peak current mode control for
easy use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output
L&C
filter.
It
compensation loop design.
With peak current mode control, the buck power
stage can be simplified to be a one-pole and one-zero
system in frequency domain. The pole is dominant
pole and can be calculated by:
greatly
simplifies
the
L
O
p
R
C
f
×
×
=
π
2
1
1
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
CO
O
Z
ESR
C
f
×
×
=
π
2
1
1
Where C
O
is the output filter capacitor;
R
is load resistor value;
ESR
is the equivalent series resistance of
output capacitor;
The compensation design is actually to shape the
converter close loop transfer function to get desired
gain
and
phase.
Several
compensation network can be used for the AOZ1013.
For most cases, a series capacitor and resistor
network connected to the COMP pin sets the pole-
zero and is adequate for a stable high-bandwidth
control loop.
In the AOZ1013, FB pin and COMP pin are the
inverting
input
and
the
transconductance error amplifier. A series R and C
compensation network connected to COMP provides
one pole and one zero. The pole is:
different
types
of
output
of
internal
VEA
C
EA
p
G
C
G
f
×
×
=
π
2
2
Where G
is the error amplifier transconductance,
which is 20010
G
is the error amplifier voltage gain,
which is 500 V/V;
C
C
is compensation capacitor;
The zero given by the external compensation network,
capacitor C
C
and resistor R
C
, is located at:
A/V;
C
C
Z
R
C
f
×
×
=
π
2
1
2
To design the compensation circuit, a target
crossover frequency f
for close loop must be
selected. The system crossover frequency is where
control loop has unity gain. The crossover frequency
is also called the converter bandwidth. Generally a
higher bandwidth means faster response to load
transient. However, the bandwidth should not be too
high because of system stability concern. When
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. The AOZ1013
operates at a fixed switching frequency range from
350kHz to 600kHz. It is recommended to choose a
crossover frequency less than 30kHz.
f
C
30
=
kHz
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